VFMADD132BF16

VFMADD132BF16 computes op1 times op3 plus op2 for each bfloat16 element, 8, 16 or 32 of them, rounds once and writes the result over op1. It belongs to AVX10.2, with the same fixed rules as VADDBF16, whose page covers the format: rounding to nearest even, denormal inputs and results taken as zeros, no exceptions and no MXCSR. The 132, 213 and 231 orders work as VFMADD231PS explains for singles. Its opcode is 98h in EVEX map 6 with no prefix and W0; VFMADD132PH has the same byte with 66.

Twelve forms#

The AVX10.2 specification (revision 7.0) describes twelve forms in one entry: the add, the subtract and the two negated versions, each in the three orders, at opcodes 98h, 9Ah, 9Ch and 9Eh for 132 and 10h and 20h higher for 213 and 231. VFMSUB132BF16, VFNMADD132BF16 and VFNMSUB132BF16 are the other 132 forms. Unlike the FP16 set it has no alternating VFMADDSUB or VFMSUBADD and no scalar form. Under merge masking an element whose mask bit is clear keeps op1, as VFMADD132PH’s page explains, and only op3 may come from memory or be broadcast from 16 bits.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles _mm512_mask_fmadd_pbh(a, k, b, c), which keeps a where the mask is clear, to vfmadd132bf16 zmm0 {k1}, zmm2, zmm1, and _mm512_fmadd_pbh(a, _mm512_set1_pbh(*p), b) to VFMADD132BF16 with word ptr [rdi]{1to32} as op3. The unmasked intrinsic and the loop Z[i] = X[i] * Y[i] + Z[i] over global __bf16 arrays take VFMADD213BF16 instead, the multiply and add contracted by default. A single __bf16 a * b + c is widened to singles and computed with a single-precision FMA, then narrowed with VCVTNEPS2BF16: it rounds twice where VFMADD132BF16 rounds once. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.bf16[i]
        b = zmm2.bf16[i]
        c = src3.bf16[i]
        zmm1.bf16[i] = fmadd(a, c, b)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD132BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS

All 96 AVX10.2 instructions