VFMADD132PD

VFMADD132PD computes op1 × op3 + op2 for each double and rounds once: the double form of VFMADD132PS, whose page shows GCC 14 choosing the 132 form for loops where Clang 23 takes VFMADD213PD; in our builds over double arrays the two compilers split the same way. VFMADD231PS explains the three digits. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, a multiplier of one double broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

Recorded on Zen 5#

• With MXCSR at 3FC0H (round down), vfmadd132pd xmm7, xmm11, xmm7 had the signaling NaN 7FF0000000012345H in both factors and the quiet NaN FFF8000000000005H in the addend, and returned the factor’s NaN made quiet, 7FF8000000012345H, setting IE: Intel’s table of FMA results ranks the factors’ NaNs above the addend’s (Volume 1, Table 14-17). In the high double, 1 × 1 plus -1 gave -0, the sign of an exact zero when rounding down.
• Under 5FC0H (round up), {evex} vfmadd132pd xmm9, xmm9, xmm14 added 1 to 1 × 2^-53, half a unit in the last place, and returned the next double after 1, 3FF0000000000001H; rounding to nearest would have given 1.
• Under DF80H (round up, FTZ), vfmadd132pd ymm1, ymm2, ymm3 turned 10^-300 × 10^-300 + 0 into +0 rather than the smallest denormal: FTZ returns zero for a tiny result whatever the rounding direction. It set UE and PE.
• Under 7F80H (toward zero), vfmadd132pd xmm7, xmm11, xmmword ptr [mem] gave the largest finite double for 10^300 × 10^300 - 10^300, an overflow that rounding toward zero stops short of infinity.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        zmm1.f64[i] = fmadd(a, c, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD132PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADD132PS
• VFMADD132SD
• VFMADD132SS
• VFMADD213PD
• VFMADD213PS
• VFMADD213SD
• VFMADD213SS
• VFMADD231PD
• VFMADD231PS
• VFMADD231SD
• VFMADD231SS
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD

All 60 FMA instructions

More AVX10.1 instructions

• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD

All 686 AVX10.1 instructions