VFMADD132PH

VFMADD132PH computes op1 times op3 plus op2 for each half-precision element and rounds once, writing the result over op1. It belongs to AVX512-FP16 (AVX10.1), like VADDPH, whose page covers the format, the CPUID bits and the encoding; the 132, 213 and 231 orders work as VFMADD231PS explains for singles, here on 32 elements per zmm register. The family is complete for halves: VFMSUB132PH, the negated VFNMADD132PH and VFNMSUB132PH, the alternating VFMADDSUB132PH and VFMSUBADD132PH, and the scalar VFMADD132SH.

The order decides what a mask keeps#

Under merge masking an element whose mask bit is clear keeps op1. In the 132 form op1 is a factor, in the 213 form the other factor, in the 231 form the addend. So _mm512_mask_fmadd_ph(a, k, b, c), whose unselected elements must stay a, the first factor, maps to the 132 or 213 order, and _mm512_mask3_fmadd_ph(a, b, c, k), which keeps c, to 231. The only operand that may come from memory, or be broadcast from a single half, is op3, a factor in the 132 order.

In compiled code#

With -march=sapphirerapids, GCC 14 compiles c[i] = a[i] * b[i] + c[i] over global _Float16 arrays to VFMADD132PH with a factor from memory, at -O2 as at -O3, and so it does for 1,024 elements through restrict pointers. Pointers without restrict keep the loop scalar at -O2, with VFMADD132SH, even for that count, and so does a count known only at run time or one such as 1,001, even over global arrays; at -O3 it vectorizes them all and finishes the remainder with VFMADD132SH. Clang 23 vectorizes them at -O2 and picks VFMADD213PH instead. Both contract the multiply and the add by default here. Without AVX512-FP16, as with -march=znver5, they widen the three operands with VCVTPH2PS, use a single-precision FMA and narrow the result with VCVTPS2PH.

Complex numbers#

VFMADDCPH and VFCMADDCPH treat pairs of halves as complex numbers and do a complex multiply-add. Intel’s optimization manual explains that the hardware runs them as a sequence of FMA steps, each rounded to FP16, so their result carries more error than one rounding (Sections 18.4.3 and 18.5.3). VFMADD132PH itself is correctly rounded, and FP16 arithmetic handles denormals at full speed with MXCSR.DAZ and FTZ ignored (Section 18.5.4).

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fmadd(a, c, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD132PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH

All 686 AVX10.1 instructions