VFMADD213PH

VFMADD213PH computes op2 × op1 + op3 for each half-precision element and rounds once, writing over op1: the destination is a factor and the addend is the operand that may come from memory or be broadcast from a single half. VFMADD132PH covers the FP16 family, what a merge mask keeps in each order and the error of the complex forms; VFMADD213PS is the single-precision form, and VADDPH explains the format and the CPUID bits. Like the other FP16 arithmetic, it rounds by MXCSR.RC or by {er} on the 512-bit register form, and ignores DAZ and FTZ (Intel’s optimization manual, Section 18.5.4).

A constant addend#

The 213 order fits a polynomial evaluated by Horner’s rule, p = p × x + c, where each result is multiplied again and the coefficient comes from memory. At -O2 with -march=x86-64-v4 -mavx512fp16, _mm512_fmadd_ph(x, y, _mm512_set1_ph(1.0f16)) compiles in GCC 14 and Clang 23 to one VFMADD213PH whose addend is the half 1.0 broadcast from memory ({1to32}), with no register spent on the constant.

Clang’s choice#

Clang 23 uses the 213 order for most contracted loops over _Float16 arrays: c[i] = a[i] * b[i] + d[i] and c[i] += a[i] * b[i] both become VFMADD213PH on ymm registers with both factors in registers and the addend read from memory, and the quadratic (x*3+2)*x+1 takes two VFMADD213PH per vector with the coefficients broadcast once into registers before the loop. GCC 14 compiles the same loops and _mm512_fmadd_ph on three registers to VFMADD132PH. Both orders give the same result, so the choice only shows where the memory operand and the destination can go.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADD213PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fmadd(b, a, c)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD213PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH

All 686 AVX10.1 instructions