VFMADD213SH

VFMADD213SH computes op2 × op1 + op3 on the low halves and rounds once: op1 is a factor and is overwritten, and op3, the operand that may come from memory, is the addend. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFMADD213PH; VFMADD132SH and VFMADD231SH are the other operand orders, VFMADD132PH explains what a merge mask keeps in each, and VADDPH covers the format and the CPUID bits. The encoding is A9h with the 66 prefix in EVEX map 6; it takes {er} between registers and reads two bytes from memory.

Constants and polynomials#

An addend read from memory is the 213 order’s use. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile x * y + 1 on _Float16 values to VFMADD213SH with the constant 1.0 read from memory, and x * y + a[5] the same way. A polynomial in Horner form, ((x * 3 + 2) * x + 1) * x + 5, becomes a chain of three VFMADD213SH in GCC, each adding the next coefficient from memory to the running value times x; Clang loads 3 first and chains the same way. A factor read from memory gives the 132 order instead.

With all three operands in registers, Clang 23 uses VFMADD213SH for x * y + z, __builtin_fmaf16 and _mm_fmadd_sh, and in its scalar loop over pointers it reads the addend in place; GCC 14 picks VFMADD132SH for all of these, as that page shows. Either order keeps the first factor in the destination, which is what the masked intrinsics _mm_mask_fmadd_sh and _mm_maskz_fmadd_sh need.

Each step of such a chain rounds once, which Intel’s optimization manual counts as correct rounding, to 0.5 ULP when rounding to nearest (Section 18.5.3); a separate multiply and add would round twice.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADD213SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fmadd(b, a, c)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD213SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH

All 686 AVX10.1 instructions