Instruction
VFMADD213SS
Fused multiply-add of the low singles: second times first plus third, into the first; the rest is unchanged.
- Extensions
- Forms
- 4 (2 VEX, 2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VFMADD213SS xmm, xmm, m32
VFMADD213SS_XMMdq_XMMd_MEMd | VEX.LIG.66.0F38.W0 A9 /r | FMA + AVX |
VFMADD213SS xmm, xmm, xmm
VFMADD213SS_XMMdq_XMMd_XMMd | VEX.LIG.66.0F38.W0 A9 /r | FMA + AVX |
VFMADD213SS xmm {k}{z}, xmm, xmm, {er}
VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | EVEX.LIG.66.0F38.W0 A9 /r | AVX10.1 or AVX512F |
VFMADD213SS xmm {k}{z}, xmm, m32
VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | EVEX.LIG.66.0F38.W0 A9 /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VFMADD213SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_fmadd_round_ss
__m128 _mm_fmadd_round_ss(__m128 A, __m128 B, __m128 C, const int R) |
|
_mm_fmadd_ss
__m128 _mm_fmadd_ss(__m128 __A, __m128 __B, __m128 __C) |
|
_mm_mask_fmadd_round_ss
__m128 _mm_mask_fmadd_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int R) |
|
_mm_mask_fmadd_ss
__m128 _mm_mask_fmadd_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) |
|
_mm_maskz_fmadd_round_ss
__m128 _mm_maskz_fmadd_round_ss(__mmask8 U, __m128 A, __m128 B, __m128 C, const int R) |
|
_mm_maskz_fmadd_ss
__m128 _mm_maskz_fmadd_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
FMA | FMA + AVX | Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_SCALAR | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
- VEXTRACTPS
- VFCMADDCPH
- VFCMADDCSH
- VFCMULCPH
- VFCMULCSH
- VFIXUPIMMPD
- VFIXUPIMMPS
- VFIXUPIMMSD
- VFIXUPIMMSS
- VFMADD132PD
- VFMADD132PH
- VFMADD132PS
- VFMADD132SD
- VFMADD132SH
- VFMADD132SS
- VFMADD213PD
- VFMADD213PH
- VFMADD213PS
- VFMADD213SD
- VFMADD213SH
- VFMADD231PD
- VFMADD231PH
- VFMADD231PS
- VFMADD231SD
- VFMADD231SH
- VFMADD231SS
- VFMADDCPH
- VFMADDCSH
- VFMADDSUB132PD
- VFMADDSUB132PH
- VFMADDSUB132PS
- VFMADDSUB213PD
- VFMADDSUB213PH
- VFMADDSUB213PS
- VFMADDSUB231PD
- VFMADDSUB231PH
- VFMADDSUB231PS
- VFMSUB132PD
- VFMSUB132PH
- VFMSUB132PS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.