VFMADD231PD

VFMADD231PD computes op2 × op3 + op1 for each double and rounds once: the accumulator form, acc += x × y, with the running sum in the destination. VFMADD231PS explains the three-digit names, the single rounding and the latency trap of a reduction, and VFMADD213PD shows the single rounding in recorded doubles. What this page adds is where compilers use the 231 form and where they do not.

Sums in registers, sums in memory#

The 231 form needs its addend in a register, since only operand 3 may come from memory. In our builds at -O2 with -ffast-math, a dot product of two double arrays shows it:

• Clang 23 keeps four ymm accumulators for -march=x86-64-v3 and x86-64-v4, and zmm ones for znver5, alternating VFMADD231PD with VFMADD132PD, which writes the new sum to the register that held one factor and so saves a register copy.
• GCC 14 keeps VMULPD and VADDPD in the loop for x86-64-v3 and znver5, and uses VFMADD231PD on one zmm accumulator for x86-64-v4.

When the sum lives in memory, as in acc[i] += x[i] * y[i], neither compiler picks 231, even without -ffast-math: Clang uses VFMADD213PD with acc[i] as operand 3, GCC VFMADD132PD with y[i] there.

Which NaN comes back#

Intel’s table of FMA results (Volume 1, Table 14-17) ranks the NaNs by their role, x × y + z: the multiplicand x first, then the multiplier y, then the addend z, quieted. In vfmadd231pd dst, op2, op3, that is op2, then op3, then the destination’s old value. On Zen 5, vfmadd231pd ymm12, ymm6, ymm6 with a signaling NaN in both factors and FFF8000000000005H in the addend returned 7FF8000000012345H, the factor’s NaN made quiet.

Rounding in the instruction#

In the 512-bit register form an {er} rounding replaces MXCSR’s and reports no exceptions. With invalid and overflow unmasked (MXCSR 6600H), Zen 5 ran vfmadd231pd zmm9{k2}, zmm9, zmm14, {rd-sae} without a fault: infinity × 0 + infinity gave the default NaN FFF8000000000000H, and the largest double × 2 plus itself gave the largest double, not infinity, as rounding down does with an overflow.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        zmm1.f64[i] = fmadd(b, c, a)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD231PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADD132PD
• VFMADD132PS
• VFMADD132SD
• VFMADD132SS
• VFMADD213PD
• VFMADD213PS
• VFMADD213SD
• VFMADD213SS
• VFMADD231PS
• VFMADD231SD
• VFMADD231SS
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD

All 60 FMA instructions

More AVX10.1 instructions

• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD

All 686 AVX10.1 instructions