VFMADD231PH

VFMADD231PH computes op2 × op3 + op1 for each half-precision element and rounds once: the destination is the addend, so it is the form that accumulates, acc += x × y, with one factor from memory or broadcast from a single half. VFMADD132PH covers the FP16 family and its masking, VFMADD231PS explains the three digits for singles, and VADDPH the format and the CPUID bits. Under a merge mask the unselected elements keep the addend, which is why both GCC 14 and Clang 23 compile _mm512_mask3_fmadd_ph(a, b, c, k), which must keep c, to it.

Dot products in halves#

A sum of products held in a half quickly runs out of precision: only integers up to 2048 are exact (Intel’s optimization manual, Section 18.5.2), so past that an addition of 1 is lost. At -O2 with -march=x86-64-v4 -mavx512fp16, a dot product over two _Float16 arrays shows how the compilers keep C’s order of additions: GCC multiplies 32 pairs at a time with VMULPH and then adds the products one by one with VADDSH, so nothing is fused; Clang keeps a chain of scalar FMAs (VFMADD231SH and VFMADD132SH) reading b from memory. Only with -ffast-math do both accumulate with VFMADD231PH, GCC in two zmm accumulators and Clang in four ymm ones, and reduce them with VADDPH at the end.

AVX10.2 adds VDPPHPS for this case: it multiplies pairs of halves and accumulates them into singles, with round to nearest even, output denormals flushed and MXCSR neither read nor written.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADD231PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fmadd(b, c, a)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD231PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH

All 686 AVX10.1 instructions