VFMADD231SS

VFMADD231SS computes op2 × op3 + op1 for the low single and rounds once: the accumulator form of VFMADD231PS, whose page explains the three digits and the single rounding. Singles 1 to 3 of the destination keep their values and bits 511:128 are cleared, so the upper singles come from op1, the register that is both a source and the destination. The VEX form needs the FMA extension, the EVEX form AVX-512F or AVX10.1; the EVEX form exists only for xmm registers and takes a rounding mode in the instruction there, where the packed forms need 512-bit registers for one. VFMADD231SD is the double form.

From C#

In our builds at -O2 with -march=x86-64-v3 or -v4, GCC 14 compiles the loop s = fmaf(x[i], y[i], s) over float arrays to VFMADD231SS, s in a register and y[i] from memory. Clang 23 unrolls it by eight: two VFMADD231SS, then VFMADD132SS steps that write each new sum into the register just loaded with x[i], so the sum moves between two registers without a copy. Without the FMA extension, at the x86-64 baseline or -v2, fmaf stays a call to the C library.

A plain a * b + c is fused as the contraction setting allows: GCC fuses it in its default GNU C mode, not with -std=c17 or -ffp-contract=off; Clang within one expression, also with -std=c17, not with -ffp-contract=off.

Masking acts on the low single only. _mm_mask3_fmadd_ss(a, b, c, k) keeps c’s low single where bit 0 of k is clear, so c must be the destination: with -march=x86-64-v4 both compilers emit vfmadd231ss xmm2{k1}, xmm0, xmm1 and a VMOVAPS of the result.

Recorded on Zen 5#

• Infinity × 0 plus the quiet NaN 7FC12345H, in vfmadd231ss xmm7, xmm11, dword ptr [mem] under MXCSR 7F80H, returned that NaN and set no IE, as Intel’s table of FMA results (Volume 1, Table 14-17) has it for a quiet NaN addend.
• vfmadd231ss xmm7{k7}, xmm12, xmm7, {rn-sae}, with signaling NaNs in op1 and op3 and invalid unmasked (MXCSR 6600H), returned the quiet NaN 7FC12345H without a fault.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm1.f32[0]
    b = xmm2.f32[0]
    c = src3.f32[0]
    xmm1.f32[0] = fmadd(b, c, a)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
# xmm1.d[1] to [3] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADD231SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADD132PD
• VFMADD132PS
• VFMADD132SD
• VFMADD132SS
• VFMADD213PD
• VFMADD213PS
• VFMADD213SD
• VFMADD213SS
• VFMADD231PD
• VFMADD231PS
• VFMADD231SD
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD

All 60 FMA instructions

More AVX10.1 instructions

• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS

All 686 AVX10.1 instructions