VFMADDCPH

VFMADDCPH multiplies the complex numbers of its two sources, pairs of halves with the real part in the even element, and adds each product to the complex number already in the destination: acc += x × y for 16 complex values per zmm register. Intel’s optimization manual describes it as two fused multiply-adds for each part, the real part acc + ac - bd and the imaginary part acc + ad + bc, each rounded to FP16 before the next, so the result carries a little more error than one rounding (Sections 18.4.3 and 18.5.3). VFMULCPH covers the layout, the masking and broadcast per pair and the #UD when the destination is also a source; VFCMADDCPH uses the conjugate of the second source, and VFMADDCSH works on the lowest pair. Its encoding is opcode 56h with the F3 prefix in EVEX map 6.

The accumulator is the destination#

Like VFMADD231PH, the instruction keeps its addend in the destination, but there is no other operand order to choose. _mm512_mask3_fmadd_pch(a, b, c, k), which keeps c where a mask bit is clear, maps to it directly. _mm512_mask_fmadd_pch(a, k, b, c) must keep a, a factor, so at -O2 with -march=x86-64-v4 -mavx512fp16 GCC 14 and Clang 23 both compute the masked product into c’s register and then merge it into a with a masked VMOVAPS. The unmasked _mm512_fmadd_pch also ends with a move in both, since the sum builds up in c’s register and is returned in that of a.

Loops over complex halves#

z[i] += x[i] * y[i] over _Complex _Float16 arrays stays scalar in both compilers by default, with a call to the library’s __mulhc3 for a NaN product. With -ffast-math, GCC vectorizes it to VFMADDCPH on zmm registers, the old z as the accumulator and x from memory; with only -fcx-limited-range it keeps the multiply and the add apart, as VFMULCPH and VADDPH. Clang splits the real and imaginary parts instead and, with -ffast-math, combines them with VFMADD231PH and VFNMADD231PH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADDCPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if zmm1.number == zmm2.number:
    fault(UD)
if not src3.is_memory:
    if zmm1.number == src3.number:
        fault(UD)
for i in range(VL // 32):
    if k1[i]:
        ar = zmm2.f16[2 * i]
        ai = zmm2.f16[2 * i + 1]
        br = src3.f16[2 * i]
        bi = src3.f16[2 * i + 1]
        x = zmm1.f16[2 * i]
        y = zmm1.f16[2 * i + 1]
        x = fmadd(ar, br, x)
        y = fmadd(ai, br, y)
        x = fnmadd(ai, bi, x)
        y = fmadd(ar, bi, y)
        zmm1.d[i] = y << 16 | x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# x + y*i += (ar + ai*i)(br + bi*i)
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADDCPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD

All 686 AVX10.1 instructions