VFMADDCSH

VFMADDCSH multiplies the lowest complex numbers of its two sources, each a pair of halves in bits 31:0, and adds the product to the pair in the destination: for a + bi times c + di the real part gains ac - bd and the imaginary part ad + bc, with a rounding to FP16 after each internal step, as VFMADDCPH describes for the packed form. VFMULCSH covers the 32-bit scalar, the mask bit per pair and the #UD when the destination is also a source; VFCMADDCSH conjugates the second factor, and VADDPH covers the format and the CPUID bits. The encoding is 57h with the F3 prefix in EVEX map 6, and register forms take {er}.

The upper bits come from a factor#

The destination is the accumulator, but Intel’s entry copies bits 127:32 of the result from the first source, a factor, and not from the destination as the real scalar FMAs such as VFMADD231SH keep them. The intrinsics follow the instruction: _mm_fmadd_sch(a, b, c) returns the sum in the low pair and the rest of a above it.

That shows in the masked forms. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile _mm_mask3_fmadd_sch(a, b, c, k), which must return c where the mask bit is clear and so keep c’s upper bits, to VFMADDCSH on a copy of c and then merge the low 32 bits back into c, Clang with a VBLENDPS and GCC with a VMOVSS. _mm_mask_fmadd_sch(a, k, b, c), which keeps a, computes into c’s register under the mask and then moves the low pair into a with a masked move.

No C expression on _Complex _Float16 values gave VFMADDCSH in our builds: scalar complex arithmetic uses real multiplies and FMAs, also with -ffast-math, and only the vectorized loops on VFMADDCPH’s page use a complex FMA.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADDCSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if xmm1.number == xmm2.number:
    fault(UD)
if not src3.is_memory:
    if xmm1.number == src3.number:
        fault(UD)
if k1[0]:
    ar = xmm2.f16[0]
    ai = xmm2.f16[1]
    br = src3.f16[0]
    bi = src3.f16[1]
    x = xmm1.f16[0]
    y = xmm1.f16[1]
    x = fmadd(ar, br, x)
    y = fmadd(ai, br, y)
    x = fnmadd(ai, bi, x)
    y = fmadd(ar, bi, y)
    xmm1.d[0] = y << 16 | x
elif zeroing:
    xmm1.d[0] = 0
# else: xmm1.d[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# x + y*i += (ar + ai*i)(br + bi*i)
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADDCSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH

All 686 AVX10.1 instructions