VFMADDSUB132PH

VFMADDSUB132PH computes op1 × op3 ∓ op2 for each half-precision element and rounds once: the even elements (0, 2, 4 …) subtract op2 and the odd ones add it, the result going over op1. The destination and the operand that may come from memory, or be broadcast from one half, are the factors. VFMADDSUB231PS explains the alternating family for singles and its use for complex numbers, VFMSUBADD132PH is the mirror form, adding in the even elements, and VFMADD132PH covers the FP16 FMAs and what a merge mask keeps in each order. The opcode is 96h with the 66 prefix in EVEX map 6, the byte of VFMADDSUB132PS in map 0F38. Rounding follows MXCSR.RC, or {er} on the 512-bit register form, and DAZ and FTZ are ignored (Intel’s optimization manual, Section 18.5.4). The SDM’s description of the instruction points to Table 5-10 for the operand orders, which is VFMSUBADD’s table; its own is Table 5-7.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, without -ffast-math, GCC 14 fuses a loop that alternates by hand over global _Float16 arrays, r[i] = a[i] * b[i] - c[i] then r[i+1] = a[i+1] * b[i+1] + c[i+1], into VFMADDSUB132PH on zmm registers with b[i] read from memory. Clang 23 fuses it too, into VFMADDSUB213PH on ymm registers, although for the same loop over floats it negates every other c[i] and uses plain FMAs, as VFMADDSUB132PS’s page shows.

From the intrinsic _mm512_fmaddsub_ph(a, b, c), GCC takes the 132 order on three registers and Clang the 213 one; with the second operand loaded from memory both read it in place with VFMADDSUB132PH, and _mm512_mask_fmaddsub_ph(a, k, b, c), which keeps a where the mask is clear, is VFMADDSUB132PH in both.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADDSUB132PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        if i % 2 == 0:
            zmm1.f16[i] = fmsub(a, c, b)
        else:
            zmm1.f16[i] = fmadd(a, c, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADDSUB132PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD

All 686 AVX10.1 instructions