VFMADDSUB213PH

VFMADDSUB213PH computes op2 × op1 ∓ op3 for each half-precision element and rounds once: the even elements subtract op3, the operand that may come from memory or be broadcast from one half, and the odd ones add it, the result going over op1. VFMADDSUB132PH covers the alternating FP16 forms, VFMADD213PH the operand roles of the 213 order, and VFMADDSUB213PS is the single-precision form. The opcode is A6h with the 66 prefix in EVEX map 6; rounding follows MXCSR.RC, or {er} on the 512-bit register form, and denormals are kept whatever DAZ and FTZ say, as VADDPH explains.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 compiles a loop that alternates by hand over _Float16 arrays, r[i] = a[i] * b[i] - c[i] then r[i+1] = a[i+1] * b[i+1] + c[i+1], to VFMADDSUB213PH on ymm registers with c read from memory; GCC 14 uses the 132 order on zmm registers. Clang also takes this order for _mm512_fmaddsub_ph(a, b, c) on three registers, and when all three operands are loaded from arrays it reads the third in place. Both compilers use VFMADDSUB213PH when only the third operand is in memory.

A constant third operand shows a difference in the other direction. For _mm512_fmaddsub_ph(x, y, _mm512_set1_ph(1.0f16)), which subtracts 1 from x × y in the even elements and adds it in the odd ones, Clang reads the half 1.0 with {1to32} as op3. GCC broadcasts it into a register first with VPBROADCASTW and uses VFMADDSUB132PH, although for _mm512_fmsub_ph with the same constant it does fold the broadcast, as VFMSUB213PH’s page shows.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADDSUB213PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        if i % 2 == 0:
            zmm1.f16[i] = fmsub(b, a, c)
        else:
            zmm1.f16[i] = fmadd(b, a, c)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADDSUB213PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD

All 686 AVX10.1 instructions