VFMADDSUB213PS

VFMADDSUB213PS computes op2 × op1 ∓ op3 for each single, rounded once: the even elements subtract op3, the operand that may come from memory, and the odd ones add it. VFMADDSUB231PS covers the alternating family and its use for complex products, and VFMADD213PS the operand roles of the 213 form. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, an addend of one single broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

In our builds#

At -O2 over float arrays, with k a float parameter, GCC 14 compiles r[i] = a[i] * k - c[i] then r[i+1] = a[i+1] * k + c[i+1] to VFMADDSUB213PS: a[i] loaded into the destination, k broadcast into a register, c[i] from memory, on ymm registers for -march=x86-64-v3 and zmm for -v4. Clang 23 negates every other c[i] with VXORPS and uses VFMADD231PS. From the intrinsic _mm256_fmaddsub_ps with all three operands loaded from arrays, Clang picks VFMADDSUB213PS with the third from memory, where GCC takes VFMADDSUB132PS.

Infinities on Zen 5#

In vfmaddsub213ps zmm14{k2}, zmm8, zmm29, {rd-sae}, with MXCSR at 6600H and invalid unmasked:

• element 0, even: infinity × 1 - (-infinity) gave plus infinity, as subtracting minus infinity adds it;
• element 15, odd: the largest single × 2 + (-infinity) gave minus infinity, the finite product making no difference;
• element 13, odd: 1 × 1 + (-1) gave -0, the sign rounding down gives an exact zero sum.

There was no fault and MXCSR kept its flags clear. In vfmaddsub213ps ymm12, ymm6, ymm6 under DF80H, by contrast, minus infinity × 2 - (-infinity) in element 6 gave the default NaN FFC00000H and set IE: there the product, minus infinity, meets plus infinity.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        if i % 2 == 0:
            zmm1.f32[i] = fmsub(b, a, c)
        else:
            zmm1.f32[i] = fmadd(b, a, c)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADDSUB213PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADD132PD
• VFMADD132PS
• VFMADD132SD
• VFMADD132SS
• VFMADD213PD
• VFMADD213PS
• VFMADD213SD
• VFMADD213SS
• VFMADD231PD
• VFMADD231PS
• VFMADD231SD
• VFMADD231SS
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD

All 60 FMA instructions

More AVX10.1 instructions

• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH

All 686 AVX10.1 instructions