VFMADDSUB231PH

VFMADDSUB231PH computes op2 × op3 ∓ op1 for each half-precision element and rounds once: the even elements subtract the destination’s old value and the odd ones add it, with one factor from memory or broadcast from a single half. VFMADDSUB231PS explains the form for singles and its use for complex products, and VFMADDSUB132PH covers the FP16 forms; under a merge mask, the unselected elements keep op1. The opcode is B6h with the 66 prefix in EVEX map 6.

One complex product#

With the real part in the even element, (a + bi)(c + di) = (ac - bd) + (ad + bc)i subtracts in the even element and adds in the odd one, the pattern of this instruction. At -O2 with -march=x86-64-v4 -mavx512fp16 -ffast-math, Clang 23 multiplies two _Complex _Float16 values with two instructions after shuffling: VMULPH computes (bd, bc) from b broadcast and the swapped pair (d, c), and VFMADDSUB231PH multiplies (c, d) by a broadcast and subtracts or adds that product, giving (ac - bd, ad + bc). GCC 14 uses scalar VMULSH and FMAs instead, as VFMULCSH’s page shows. Intel’s optimization manual describes the hardware’s own complex multiply, VFMULCPH, as the same two steps, each rounded to FP16 (Section 18.4.3).

GCC reaches the instruction in vector loops: with -ffast-math, a sum of x[i] * ~y[i] over _Complex _Float16 arrays becomes VMULPH and VFMADDSUB231PH on zmm registers, as VFCMADDCPH’s page shows, and the sum without the conjugate takes the mirror form, VFMSUBADD231PH.

Masks and accumulators#

GCC 14 and Clang 23 compile _mm512_mask3_fmaddsub_ph(a, b, c, k), which keeps c where the mask is clear, to VFMADDSUB231PH with c as destination. A loop acc = _mm512_fmaddsub_ph(x, y, acc) over loaded vectors uses it on every pass in GCC; Clang unrolls it and alternates with VFMADDSUB132PH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMADDSUB231PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        if i % 2 == 0:
            zmm1.f16[i] = fmsub(b, c, a)
        else:
            zmm1.f16[i] = fmadd(b, c, a)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMADDSUB231PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD

All 686 AVX10.1 instructions