VFMSUB132PH

VFMSUB132PH computes op1 × op3 - op2 for each half-precision element and rounds once, writing over op1: the destination and the operand that may come from memory, or be broadcast from one half, are the factors, and the middle register is subtracted. VFMSUB231PS explains the subtracting family for singles, VFMADD132PH the FP16 forms and what a merge mask keeps in each operand order, and VADDPH the format and the CPUID bits. The opcode is 9Ah with the 66 prefix in EVEX map 6, the byte of VFMSUB132PS in map 0F38. Rounding follows MXCSR.RC, or {er} on the 512-bit register form, and DAZ and FTZ are ignored (Intel’s optimization manual, Section 18.5.4).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles c[i] = a[i] * b[i] - d[i] over global _Float16 arrays to VFMSUB132PH on zmm registers with b[i] read from memory, and c[i] = a[i] * b[i] - c[i] the same way. Clang 23 uses VFMSUB213PH on ymm registers for both, with the subtracted array read from memory. _mm512_fmsub_ph(a, b, c) on three registers splits the same way, and _mm512_fmsub_round_ph with _MM_FROUND_TO_ZERO too, as {rz-sae}. _mm512_mask_fmsub_ph(a, k, b, c), whose unselected elements must keep a, is VFMSUB132PH in both, since a is a factor here.

A constant is not subtracted at all: c[i] = a[i] * b[i] - 1 becomes VFMADD132PH in both compilers, adding -1 broadcast into a register before the loop.

The single rounding counts for more in halves than in singles: with 11 significant bits, the product of two halves needs up to 22, and a separate VMULPH would drop half of them before the subtraction. Intel’s optimization manual counts the fused multiply-add among the FP16 operations that are correctly rounded (Section 18.5.3).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMSUB132PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fmsub(a, c, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB132PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD

All 686 AVX10.1 instructions