VFMSUB132SH

VFMSUB132SH computes op1 × op3 - op2 on the low halves and rounds once, writing over op1: the destination and the operand that may come from memory are the factors. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFMSUB132PH; VFMSUB213SH and VFMSUB231SH are the other operand orders, VFMADD132SH explains what the scalar FMAs keep, and VFMSUB132SS is the single-precision form. The encoding is 9Bh with the 66 prefix in EVEX map 6; it takes {er} between registers and reads two bytes from memory.

The error of a product#

With one rounding, x × y - p, where p is the product rounded to a half, gives what that rounding lost, the step that splits a product into a rounded part and an error. In halves the error is exact only while it stays a multiple of the smallest denormal, 2^-24, which holds when the exponents of x and y add up to at least -4; for smaller products the error is rounded as well. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles p = x * y; e = __builtin_fmaf16(x, y, -p) on _Float16 values to VMULSH and VFMSUB132SH, Clang 23 to VMULSH and VFMSUB213SH.

In our builds#

GCC compiles x * y - z, __builtin_fmaf16(x, y, -z) and _mm_fmsub_sh(a, b, c) to VFMSUB132SH, Clang to VFMSUB213SH; a factor read from memory, x * a[5] - z, gives VFMSUB132SH in both, and a subtrahend from memory the 213 order. x * y - 1 becomes VFMADD213SH adding -1. With -ffast-math, GCC computes the real part of a product of two _Complex _Float16 values as VMULSH followed by VFMSUB132SH, which VFMULCSH’s page describes.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMSUB132SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fmsub(a, c, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB132SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD

All 686 AVX10.1 instructions