x86-64.net

Instruction

VFMSUB132SS

Fused multiply-subtract of the low singles: first times third minus second, into the first; the rest is unchanged.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VFMSUB132SS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFMSUB132SS xmm, xmm, m32 VFMSUB132SS_XMMdq_XMMd_MEMdVEX.LIG.66.0F38.W0 9B /rFMA + AVX
VFMSUB132SS xmm, xmm, xmm VFMSUB132SS_XMMdq_XMMd_XMMdVEX.LIG.66.0F38.W0 9B /rFMA + AVX
VFMSUB132SS xmm {k}{z}, xmm, xmm, {er} VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512EVEX.LIG.66.0F38.W0 9B /rAVX10.1 or AVX512F
VFMSUB132SS xmm {k}{z}, xmm, m32 VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512EVEX.LIG.66.0F38.W0 9B /rAVX10.1 or AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB132SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fmsub_ss __m128 _mm_fmsub_ss(__m128 __A, __m128 __B, __m128 __C)

VFMSUB132SS xmm, xmm, m32 VEX.LIG -mfmawhen __B comes from memory

_mm_mask_fmsub_ss __m128 _mm_mask_fmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)

VFMSUB132SS xmm {k}, xmm, m32 EVEX.LIG -mavx512fwhen __A comes from memory

_mm_maskz_fmsub_ss __m128 _mm_maskz_fmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)

VFMSUB132SS xmm {k}{z}, xmm, m32 EVEX.LIG -mavx512fwhen __B comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
FMA

FMA + AVX
CPUID.01H:ECX[12] FMA
CPUID.01H:ECX[28] AVX

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.