Instruction
VFMSUB213BF16
Fused multiply-subtract of packed bfloat16 values: second operand times first minus third, into the first.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VFMSUB213BF16 computes op2 × op1 - op3 for each bfloat16 element, 8, 16 or 32 per register, rounds once to nearest even and writes the result over op1. It is the 213 order of AVX10.2’s multiply-subtract, one of the twelve forms that VFMADD132BF16’s page describes with their shared rules: denormal inputs and results taken as zeros, no exceptions and no MXCSR. Its opcode is AAh in EVEX map 6 with no prefix and W0; VFMSUB213PH has the same byte with 66. Only op3 may come from memory or be broadcast from 16 bits.
VFMSUB231PS explains the operation and the three orders for singles. Under merge masking an element whose mask bit is clear keeps op1, here the other factor.
In our builds
GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles
the unmasked _mm512_fmsub_pbh(a, b, c) to vfmsub213bf16 zmm0, zmm1, zmm2 and the zero-masked form to the same with {k1} {z}. It also
takes this form for the loop Z[i] = X[i] * Y[i] - Z[i] over global
__bf16 arrays, with Z read from memory as op3, the multiply and the
subtract contracted by default. No AVX10.2 processor appears in this
site’s recorded cases.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VFMSUB213BF16 xmm {k}{z}, xmm, xmm
VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 | EVEX.128.NP.MAP6.W0 AA /r | AVX10.2 |
VFMSUB213BF16 xmm {k}{z}, xmm, m128/m16bcst
VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 | EVEX.128.NP.MAP6.W0 AA /r | AVX10.2 |
VFMSUB213BF16 ymm {k}{z}, ymm, ymm
VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 | EVEX.256.NP.MAP6.W0 AA /r | AVX10.2 |
VFMSUB213BF16 ymm {k}{z}, ymm, m256/m16bcst
VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 | EVEX.256.NP.MAP6.W0 AA /r | AVX10.2 |
VFMSUB213BF16 zmm {k}{z}, zmm, zmm
VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 | EVEX.512.NP.MAP6.W0 AA /r | AVX10.2 |
VFMSUB213BF16 zmm {k}{z}, zmm, m512/m16bcst
VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 | EVEX.512.NP.MAP6.W0 AA /r | AVX10.2 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every bfloat16 works alike: 8, 16 and 32 bfloat16s in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m16bcst, one bfloat16 from memory stands for every element of the last source. The sources are drawn above the result, each element in its own column.
Result bfloat16 i comes from bfloat16 i of xmm1, xmm2 and xmm3. Result bfloat16s 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 16):
if k1[i]:
a = zmm1.bf16[i]
b = zmm2.bf16[i]
c = src3.bf16[i]
zmm1.bf16[i] = fmsub(b, a, c)
elif zeroing:
zmm1.bf16[i] = 0
# else: zmm1.bf16[i] keeps its value
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL upNot run on a processor: none of these processors has AVX10.2. The tests check its arithmetic against MPFR.
Operands
| Operand | Kind | Action |
|---|---|---|
VFMSUB213BF16 xmm {k}{z}, xmm, xmm/m128/m16bcst VFMSUB213BF16 ymm {k}{z}, ymm, ymm/m256/m16bcst VFMSUB213BF16 zmm {k}{z}, zmm, zmm/m512/m16bcst | ||
xmm, ymm, zmm | explicit | read, write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
xmm/m128/m16bcst, ymm/m256/m16bcst, zmm/m512/m16bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking; always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero
- Memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VFMSUB213BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_fmsub_pbh
__m128bh _mm_fmsub_pbh(__m128bh __A, __m128bh __B, __m128bh __C) |
|
_mm_mask_fmsub_pbh
__m128bh _mm_mask_fmsub_pbh(__m128bh __A, __mmask8 __U, __m128bh __B, __m128bh __C) |
|
_mm_maskz_fmsub_pbh
__m128bh _mm_maskz_fmsub_pbh(__mmask8 __U, __m128bh __A, __m128bh __B, __m128bh __C) |
|
_mm256_fmsub_pbh
__m256bh _mm256_fmsub_pbh(__m256bh __A, __m256bh __B, __m256bh __C) |
|
_mm256_mask_fmsub_pbh
__m256bh _mm256_mask_fmsub_pbh(__m256bh __A, __mmask16 __U, __m256bh __B, __m256bh __C) |
|
_mm256_maskz_fmsub_pbh
__m256bh _mm256_maskz_fmsub_pbh(__mmask16 __U, __m256bh __A, __m256bh __B, __m256bh __C) |
|
_mm512_fmsub_pbh
__m512bh _mm512_fmsub_pbh(__m512bh __A, __m512bh __B, __m512bh __C) |
|
_mm512_mask_fmsub_pbh
__m512bh _mm512_mask_fmsub_pbh(__m512bh __A, __mmask32 __U, __m512bh __B, __m512bh __C) |
|
_mm512_maskz_fmsub_pbh
__m512bh _mm512_maskz_fmsub_pbh(__mmask32 __U, __m512bh __A, __m512bh __B, __m512bh __C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX10_2_BF16_128 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX10_2_BF16_256 | Same as AVX10_2_BF16_128 | Same as AVX10_2_BF16_128 |
AVX10_2_BF16_512 | Same as AVX10_2_BF16_128 | Same as AVX10_2_BF16_128 |
More AVX10.2 instructions
- VCVTTPD2UDQS
- VCVTTPD2UQQS
- VCVTTPH2IBS
- VCVTTPH2IUBS
- VCVTTPS2DQS
- VCVTTPS2IBS
- VCVTTPS2IUBS
- VCVTTPS2QQS
- VCVTTPS2UDQS
- VCVTTPS2UQQS
- VCVTTSD2SIS
- VCVTTSD2USIS
- VCVTTSS2SIS
- VCVTTSS2USIS
- VDIVBF16
- VDPPHPS
- VFMADD132BF16
- VFMADD213BF16
- VFMADD231BF16
- VFMSUB132BF16
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB132BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETEXPBF16
- VGETMANTBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXPS
- VMINMAXSD
- VMINMAXSH
- VMINMAXSS
- VMOVD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.