VFMSUB213PH

VFMSUB213PH computes op2 × op1 - op3 for each half-precision element and rounds once, writing over op1: the destination is a factor, and the operand that may come from memory, or be broadcast from one half, is the one subtracted. VFMSUB132PH covers the subtracting FP16 family, VFMADD213PH the 213 order with an addend, and VFMSUB213PS the single-precision form. The opcode is AAh with the 66 prefix in EVEX map 6; rounding follows MXCSR.RC, or {er} on the 512-bit register form, and denormals are kept whatever DAZ and FTZ say, as VADDPH explains.

Clang’s order#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 compiles c[i] = a[i] * b[i] - d[i] and c[i] = a[i] * b[i] - c[i] over _Float16 arrays to VFMSUB213PH on ymm registers, both factors loaded and the subtracted array read from memory; GCC 14 uses VFMSUB132PH on zmm registers with a factor from memory. On three registers, _mm512_fmsub_ph(a, b, c) and _mm512_maskz_fmsub_ph are VFMSUB213PH in Clang and VFMSUB132PH in GCC. The result is the same either way.

A constant subtrahend#

_mm512_fmsub_ph(x, y, _mm512_set1_ph(1.0f16)) shows the two compilers treating a constant differently. GCC keeps VFMSUB213PH and reads the half 1.0 from memory with {1to32}; Clang negates the constant at compile time and emits VFMADD213PH with -1 broadcast from memory. Since x × y - 1 and x × y + (-1) are the same exact value, rounded once, the two give the same results, NaNs and signed zeros included.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMSUB213PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fmsub(b, a, c)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB213PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH
• VFMADDSUB132PD
• VFMADDSUB132PH
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH

All 686 AVX10.1 instructions