VFMSUB213SD instruction (FMA, AVX10.1)

VFMSUB213SD computes op2 × op1 - op3 for the low double, rounded once: the destination is a factor and the subtrahend is the operand that may come from memory. The high double keeps the destination’s value and bits 511:128 are cleared. VFMSUB231PS covers the subtracting family, VFMSUB213PS the 213 form, and VFMADD231SS what the scalar forms change. VFMSUB213SS is the single form.

In our builds at -O2 with -march=x86-64-v3 or -v4, Clang 23 compiles a * b - c on three double arguments to vfmsub213sd xmm0, xmm1, xmm2, where GCC 14 uses VFMSUB132SD.

Recorded on Zen 5

vfmsub213sd xmm7{k5}{z}, xmm12, qword ptr [mem] under MXCSR FFC0H (toward zero) computed the largest double × 2 minus the most negative one, three times the largest double, as the largest double, and set OE and PE.
vfmsub213sd xmm24{k7}, xmm3, xmm3, {rd-sae} computed 1 × 0 - 1 as -1.
Under 3FC0H, vfmsub213sd xmm7, xmm11, xmm7 computed infinity × the quiet NaN 7FF8000000012345H minus the same NaN and returned it with IE clear.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Every encoding of VFMSUB213SD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFMSUB213SD xmm, xmm, m64` VFMSUB213SD_XMMdq_XMMq_MEMq	`VEX.LIG.66.0F38.W1 AB /r`	FMA + AVX
`VFMSUB213SD xmm, xmm, xmm` VFMSUB213SD_XMMdq_XMMq_XMMq	`VEX.LIG.66.0F38.W1 AB /r`	FMA + AVX
`VFMSUB213SD xmm {k}{z}, xmm, xmm, {er}` VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512	`EVEX.LIG.66.0F38.W1 AB /r`	AVX10.1 or AVX512F
`VFMSUB213SD xmm {k}{z}, xmm, m64` VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512	`EVEX.LIG.66.0F38.W1 AB /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m64` `xmm {k}{z}, xmm, m64`	`xmm, xmm, xmm` `xmm {k}{z}, xmm, xmm, {er}`
Haswell, Broadwell	10 / 0.5p01	5 / 0.5p01
Skylake, Skylake-SP, Ice Lake	9 / 0.5p01	4 / 0.5p01
Alder Lake, Sapphire Rapids	11 / 0.5p01	4 / 0.5p01
Lunar Lake	10 / 2V0 V1	4 / 2V0 V1
Piledriver	10 / 1.5FPFMA FPU0 FPU1	5 / 1.5FPFMA FPU0 FPU1 FPU2 FPU3
Zen, Zen 2	12 / 0.5FPU0 FPU1	5 / 0.5FPU0 FPU1
Zen 3	11 / 0.5FP0 FP1	4 / 0.5FP0 FP1
Zen 4	11 / 1FP0 FP1	4 / 1¹FP0 FP1

Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1277; AMD 58455, row 1367).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

The write mask k1 applies to the low double: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result double 0 is computed from double 0 of xmm1, xmm2 and xmm3; double 1 is that of xmm1. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm1.f64[0]
    b = xmm2.f64[0]
    c = src3.f64[0]
    xmm1.f64[0] = fmsub(b, a, c)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
# xmm1.q[1] keeps its value
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFMSUB213SD xmm, xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm`	explicit	read
`xmm/m64`	explicit	read
`VFMSUB213SD xmm {k}{z}, xmm, xmm/m64, {er}`
`xmm`	explicit	read, write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-3
EVEX forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
EVEX forms: write masking
EVEX memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB213SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_fmsub_round_sd` `__m128d _mm_fmsub_round_sd(__m128d A, __m128d B, __m128d C, const int R)`	`VFMSUB213SD xmm, xmm, xmm, {er}` EVEX.LIG -mavx512f
`_mm_fmsub_sd` `__m128d _mm_fmsub_sd(__m128d __A, __m128d __B, __m128d __C)`	`VFMSUB213SD xmm, xmm, xmm` VEX.LIG -mfma
`_mm_mask_fmsub_round_sd` `__m128d _mm_mask_fmsub_round_sd(__m128d W, __mmask8 U, __m128d A, __m128d B, const int R)`	`VFMSUB213SD xmm {k}, xmm, xmm, {er}` EVEX.LIG -mavx512f
`_mm_mask_fmsub_sd` `__m128d _mm_mask_fmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)`	`VFMSUB213SD xmm {k}, xmm, xmm` EVEX.LIG -mavx512f
`_mm_maskz_fmsub_round_sd` `__m128d _mm_maskz_fmsub_round_sd(__mmask8 U, __m128d A, __m128d B, __m128d C, const int R)`	`VFMSUB213SD xmm {k}{z}, xmm, xmm, {er}` EVEX.LIG -mavx512f
`_mm_maskz_fmsub_sd` `__m128d _mm_maskz_fmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)`	`VFMSUB213SD xmm {k}{z}, xmm, xmm` EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`FMA` FMA	FMA + AVX `CPUID.01H:ECX[12]` FMA `CPUID.01H:ECX[28]` AVX XED and Intel’s SDM differ: XED also asks for the AVX bit, `CPUID.01H:ECX[28]`, besides FMA, `CPUID.01H:ECX[12]`. The opcode tables of revision 093 of Intel’s SDM name FMA alone for every VEX form, but its Volume 1 tells software to check for AVX first and then for FMA, so in effect the two agree. Sources: Intel XED v2026.08.23, datafiles/hswavx/cpuid.xed.txt; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026), VFMADD132PD/VFMADD213PD/VFMADD231PD and the other FMA instructions: the opcode tables, from page 5-207; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026), section 14.5.3, Detection of FMA, page 14-24.	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

FMA

FMA + AVX
CPUID.01H:ECX[12] FMA
CPUID.01H:ECX[28] AVX

XED and Intel’s SDM differ: XED also asks for the AVX bit, CPUID.01H:ECX[28], besides FMA, CPUID.01H:ECX[12]. The opcode tables of revision 093 of Intel’s SDM name FMA alone for every VEX form, but its Volume 1 tells software to check for AVX first and then for FMA, so in effect the two agree.

Sources: Intel XED v2026.08.23, datafiles/hswavx/cpuid.xed.txt; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026), VFMADD132PD/VFMADD213PD/VFMADD231PD and the other FMA instructions: the opcode tables, from page 5-207; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026), section 14.5.3, Detection of FMA, page 14-24.