x86-64.net

Instruction

VFMSUB213SS

Fused multiply-subtract of the low singles: second times first minus third, into the first; the rest is unchanged.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VFMSUB213SS computes op2 × op1 - op3 for the low single, rounded once: the destination is a factor and the subtrahend is the operand that may come from memory. Singles 1 to 3 keep the destination’s values and bits 511:128 are cleared. VFMSUB231PS covers the subtracting family, VFMSUB213PS the 213 form, and VFMADD231SS what the scalar forms change. VFMSUB213SD is the double form.

Clang’s choice

In our builds at -O2 with -march=x86-64-v3 or -v4, Clang 23 compiles a * b - c and fmaf(a, b, -c) on three float arguments to vfmsub213ss xmm0, xmm1, xmm2, and ga = ga * gb - gc over globals with gc from memory. GCC 14 uses VFMSUB132SS for these. Without contraction (-ffp-contract=off, or GCC with -std=c17) a * b - c is a VMULSS and a VSUBSS, while fmaf(a, b, -c) stays fused.

Recorded on Zen 5

  • vfmsub213ss xmm7{k5}{z}, xmm12, dword ptr [mem], under MXCSR FFC0H, computed the largest single × 2 minus minus infinity as infinity, with no flag set.
  • vfmsub213ss xmm5{k1}, xmm5, xmm5, {rd-sae}, with bit 0 of K1 clear and the quiet NaN 7FC12345H in all three operands, left the low single as it was, and MXCSR unchanged.
  • Under 7F80H, vfmsub213ss xmm8, xmm15, dword ptr [mem] computed 0.5 × -0.5 - 0.25 as -0.5, exactly.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Every encoding of VFMSUB213SS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFMSUB213SS xmm, xmm, m32 VFMSUB213SS_XMMdq_XMMd_MEMdVEX.LIG.66.0F38.W0 AB /rFMA + AVX
VFMSUB213SS xmm, xmm, xmm VFMSUB213SS_XMMdq_XMMd_XMMdVEX.LIG.66.0F38.W0 AB /rFMA + AVX
VFMSUB213SS xmm {k}{z}, xmm, xmm, {er} VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512EVEX.LIG.66.0F38.W0 AB /rAVX10.1 or AVX512F
VFMSUB213SS xmm {k}{z}, xmm, m32 VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512EVEX.LIG.66.0F38.W0 AB /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m32
xmm {k}{z}, xmm, m32		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm, {er}
Haswell, Broadwell10 / 0.5p015 / 0.5p01
Skylake, Skylake-SP, Ice Lake9 / 0.5p014 / 0.5p01
Alder Lake, Sapphire Rapids11 / 0.5p014 / 0.5p01
Lunar Lake10 / 2V0 V14 / 2V0 V1
Piledriver10 / 1.5FPFMA FPU0 FPU15 / 1.5FPFMA FPU0 FPU1 FPU2 FPU3
Zen, Zen 212 / 0.5FPU0 FPU15 / 0.5FPU0 FPU1
Zen 311 / 0.5FP0 FP14 / 0.5FP0 FP1
Zen 411 / 1FP0 FP14 / 11FP0 FP1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1280; AMD 58455, row 1370).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.
VFMSUB213SS: the low elementResult single 0 is computed from single 0 of xmm1, xmm2 and xmm3; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.0123xmm1a1k1r0a1a2a3xmm10123xmm2b0123xmm3or m32c

The write mask k1 applies to the low single: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result single 0 is computed from single 0 of xmm1, xmm2 and xmm3; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm1.f32[0]
    b = xmm2.f32[0]
    c = src3.f32[0]
    xmm1.f32[0] = fmsub(b, a, c)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
# xmm1.d[1] to [3] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VFMSUB213SS xmm, xmm, xmm/m32
xmmexplicitread, write
xmmexplicitread
xmm/m32explicitread
VFMSUB213SS xmm {k}{z}, xmm, xmm/m32, {er}
xmmexplicitread, write (masked)
{k}explicitread (write mask)
xmmexplicitread
xmm/m32explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-3
EVEX forms
AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR
EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB213SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fmsub_round_ss __m128 _mm_fmsub_round_ss(__m128 A, __m128 B, __m128 C, const int R)

VFMSUB213SS xmm, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_fmsub_ss __m128 _mm_fmsub_ss(__m128 __A, __m128 __B, __m128 __C)

VFMSUB213SS xmm, xmm, xmm VEX.LIG -mfma

_mm_mask_fmsub_round_ss __m128 _mm_mask_fmsub_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int R)

VFMSUB213SS xmm {k}, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_mask_fmsub_ss __m128 _mm_mask_fmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)

VFMSUB213SS xmm {k}, xmm, xmm EVEX.LIG -mavx512f

_mm_maskz_fmsub_round_ss __m128 _mm_maskz_fmsub_round_ss(__mmask8 U, __m128 A, __m128 B, __m128 C, const int R)

VFMSUB213SS xmm {k}{z}, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_maskz_fmsub_ss __m128 _mm_maskz_fmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)

VFMSUB213SS xmm {k}{z}, xmm, xmm EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
FMA

FMA + AVX
CPUID.01H:ECX[12] FMA
CPUID.01H:ECX[28] AVX

XED and Intel’s SDM differ: XED also asks for the AVX bit, CPUID.01H:ECX[28], besides FMA, CPUID.01H:ECX[12]. The opcode tables of revision 093 of Intel’s SDM name FMA alone for every VEX form, but its Volume 1 tells software to check for AVX first and then for FMA, so in effect the two agree.

Sources: Intel XED v2026.08.23, datafiles/hswavx/cpuid.xed.txt; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026), VFMADD132PD/VFMADD213PD/VFMADD231PD and the other FMA instructions: the opcode tables, from page 5-207; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026), section 14.5.3, Detection of FMA, page 14-24.

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More FMA instructions

All 60 FMA instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-282 (VFMSUB132SS/VFMSUB213SS/VFMSUB231SS)
  6. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
  8. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.