x86-64.net

Instruction

VFMSUB231BF16

Fused multiply-subtract of packed bfloat16 values: second operand times third minus first, into the first.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VFMSUB231BF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFMSUB231BF16 xmm {k}{z}, xmm, xmm VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512EVEX.128.NP.MAP6.W0 BA /rAVX10.2
VFMSUB231BF16 xmm {k}{z}, xmm, m128/m16bcst VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512EVEX.128.NP.MAP6.W0 BA /rAVX10.2
VFMSUB231BF16 ymm {k}{z}, ymm, ymm VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512EVEX.256.NP.MAP6.W0 BA /rAVX10.2
VFMSUB231BF16 ymm {k}{z}, ymm, m256/m16bcst VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512EVEX.256.NP.MAP6.W0 BA /rAVX10.2
VFMSUB231BF16 zmm {k}{z}, zmm, zmm VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512EVEX.512.NP.MAP6.W0 BA /rAVX10.2
VFMSUB231BF16 zmm {k}{z}, zmm, m512/m16bcst VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512EVEX.512.NP.MAP6.W0 BA /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB231BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fmsub_pbh __m128bh _mm_fmsub_pbh(__m128bh __A, __m128bh __B, __m128bh __C)

VFMSUB231BF16 xmm, xmm, xmm EVEX.128 -mavx10.2when __C is already in the destination register

_mm_mask3_fmsub_pbh __m128bh _mm_mask3_fmsub_pbh(__m128bh __A, __m128bh __B, __m128bh __C, __mmask8 __U)

VFMSUB231BF16 xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_fmsub_pbh __m128bh _mm_maskz_fmsub_pbh(__mmask8 __U, __m128bh __A, __m128bh __B, __m128bh __C)

VFMSUB231BF16 xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2when __C is already in the destination register

_mm256_fmsub_pbh __m256bh _mm256_fmsub_pbh(__m256bh __A, __m256bh __B, __m256bh __C)

VFMSUB231BF16 ymm, ymm, ymm EVEX.256 -mavx10.2when __C is already in the destination register

_mm256_mask3_fmsub_pbh __m256bh _mm256_mask3_fmsub_pbh(__m256bh __A, __m256bh __B, __m256bh __C, __mmask16 __U)

VFMSUB231BF16 ymm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_fmsub_pbh __m256bh _mm256_maskz_fmsub_pbh(__mmask16 __U, __m256bh __A, __m256bh __B, __m256bh __C)

VFMSUB231BF16 ymm {k}{z}, ymm, ymm EVEX.256 -mavx10.2when __C is already in the destination register

_mm512_fmsub_pbh __m512bh _mm512_fmsub_pbh(__m512bh __A, __m512bh __B, __m512bh __C)

VFMSUB231BF16 zmm, zmm, zmm EVEX.512 -mavx10.2when __C is already in the destination register

_mm512_mask3_fmsub_pbh __m512bh _mm512_mask3_fmsub_pbh(__m512bh __A, __m512bh __B, __m512bh __C, __mmask32 __U)

VFMSUB231BF16 zmm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_fmsub_pbh __m512bh _mm512_maskz_fmsub_pbh(__mmask32 __U, __m512bh __A, __m512bh __B, __m512bh __C)

VFMSUB231BF16 zmm {k}{z}, zmm, zmm EVEX.512 -mavx10.2when __C is already in the destination register

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_2_BF16_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX10_2_BF16_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX10_2_BF16_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.