VFMSUB231PH

VFMSUB231PH computes op2 × op3 - op1 for each half-precision element and rounds once: the product minus the destination’s old value, with one factor from memory or broadcast from a single half. As VFMSUB231PS notes for singles, this is acc = x × y - acc, not acc -= x × y, which is VFNMADD231PH. VFMSUB132PH covers the subtracting FP16 family and VFMADD132PH what a merge mask keeps in each order: here the unselected elements keep the value subtracted. The opcode is BAh with the 66 prefix in EVEX map 6.

Complex products#

The real part of a complex product, a.re × b.re - a.im × b.im, is one multiplication and one fused subtraction, which is how Intel’s optimization manual describes the hardware’s own complex multiply: a multiply followed by an FMA, each step rounded to FP16 (Section 18.4.3). At -O2 with -march=x86-64-v4 -mavx512fp16 -ffast-math, Clang 23 compiles a loop of products of _Complex _Float16 arrays that way: it separates the real and imaginary halves, computes a.im × b.im with VMULPH and subtracts it from a.re × b.re with VFMSUB231PH, while VFMADD231PH builds the imaginary part. For x[i] * ~y[i], the product with the conjugate, it is the imaginary part that takes VFMSUB231PH. GCC 14 uses VFMULCPH and VFCMULCPH for these loops instead.

Masks#

GCC 14 and Clang 23 compile _mm512_mask3_fmsub_ph(a, b, c, k), which must keep c where the mask bit is clear, to VFMSUB231PH with c as the destination, followed by a move to the return register; the other masked forms keep a factor and use the 132 or 213 order.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMSUB231PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fmsub(b, c, a)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB231PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PH
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH

All 686 AVX10.1 instructions