Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VFMSUB231PS computes op2 × op3 - op1 for each single, rounded once: the product minus the destination’s old value. It works as VFMADD231PS does, with the addend’s sign flipped, and VFNMADD231PS sets the four sign variants of the FMA family side by side. Note the order: the 231 form subtracts the accumulator from the product, so acc = x × y - acc, which is rarely what a loop wants; acc -= x × y is VFNMADD.

The error of a product

With one rounding, x × y - p, where p is the product rounded to a single, gives exactly what that rounding lost: the classic way to split a product into a rounded part and an error. The cases recorded on Zen 5 show the effect of the single rounding. For vfmsub231ps ymm4, ymm4, ymm4, x × x - x with x = 1 + 2^-12 is 2^-12 + 2^-24, and Zen 5 returned that exactly, 39800800H. Rounding to nearest, a VMULPS would first turn x × x = 1 + 2^-11 + 2^-24 into 1 + 2^-11, and the subtraction would then give 2^-12, the 2^-24 lost.

In our builds at -O2 with -march=x86-64-v3, the loop e[i] = fmaf(x[i], y[i], -p[i]) becomes VFMSUB213PS in Clang 23 and VFMSUB132PS in GCC 14, each with the operand from memory that suits it; acc[i] = x[i] * y[i] - acc[i] compiles the same way.

In complex products

The real part of a complex product, a.re × b.re - a.im × b.im, is one multiplication and one fused subtraction. With -ffast-math, Clang compiles a loop of _Complex float products for -march=x86-64-v3 by separating the real and imaginary parts, then VMULPS for a.im × b.im and VFMSUB231PS for the rest, with VFMADD231PS doing the imaginary part; GCC uses VFMADDSUB231PS on the interleaved values instead.

DAZ on the subtrahend

The {evex} form recorded with MXCSR.DAZ set and FTZ clear computed 2^-126 × 0.5 - 2^-149 as 2^-127: the denormal 2^-149 counted as zero, while the denormal result itself was kept, as DAZ applies to inputs and FTZ to results.

Forms

Every encoding of VFMSUB231PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFMSUB231PS xmm, xmm, m128 VFMSUB231PS_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.W0 BA /rFMA + AVX
VFMSUB231PS xmm, xmm, xmm VFMSUB231PS_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.W0 BA /rFMA + AVX
VFMSUB231PS ymm, ymm, m256 VFMSUB231PS_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.W0 BA /rFMA + AVX
VFMSUB231PS ymm, ymm, ymm VFMSUB231PS_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.W0 BA /rFMA + AVX
VFMSUB231PS zmm {k}{z}, zmm, zmm, {er} VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512EVEX.512.66.0F38.W0 BA /rAVX10.1 or AVX512F
VFMSUB231PS zmm {k}{z}, zmm, m512/m32bcst VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512EVEX.512.66.0F38.W0 BA /rAVX10.1 or AVX512F
VFMSUB231PS xmm {k}{z}, xmm, xmm VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512EVEX.128.66.0F38.W0 BA /rAVX10.1 or AVX512F + AVX512VL
VFMSUB231PS xmm {k}{z}, xmm, m128/m32bcst VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512EVEX.128.66.0F38.W0 BA /rAVX10.1 or AVX512F + AVX512VL
VFMSUB231PS ymm {k}{z}, ymm, ymm VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512EVEX.256.66.0F38.W0 BA /rAVX10.1 or AVX512F + AVX512VL
VFMSUB231PS ymm {k}{z}, ymm, m256/m32bcst VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512EVEX.256.66.0F38.W0 BA /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m32bcst
xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm
ymm, ymm, m256
ymm {k}{z}, ymm, m256/m32bcst
ymm, ymm, ymmzmm {k}{z}, zmm, zmm, {er}zmm {k}{z}, zmm, m512/m32bcst
Haswell11 / 0.5p015 / 0.5p0112 / 0.5p015 / 0.5p01
Broadwell10 / 0.5p015 / 0.5p0111 / 0.5p015 / 0.5p01
Skylake10 / 0.5p014 / 0.5p0111 / 0.5p014 / 0.5p01
Skylake-SP10 / 0.5p014 / 0.5p0111 / 0.5p014 / 0.5p014 / 0.5p0511 / 0.5p05
Ice Lake10 / 0.5p014 / 0.5p0111 / 0.5p014 / 0.5p014 / 1p011 / 1p0
Alder Lake11 / 0.5p014 / 0.5p0112 / 0.5p014 / 0.5p01
Sapphire Rapids11 / 0.5p014 / 0.5p0112 / 0.5p014 / 0.5p014 / 1p012 / 1p0
Lunar Lake10 / 2V0 V14 / 2V0 V111 / 2.33V0 V14 / 2V0 V1
Piledriver10 / 1.5FPFMA FPU0 FPU15 / 1.5FPFMA FPU0 FPU1 FPU2 FPU310 / 1.5FPFMA FPU0 FPU15 / 1.5FPFMA FPU0 FPU1 FPU2 FPU3
Zen12 / 0.5FPU0 FPU15 / 0.5FPU0 FPU112 / 1FPU0 FPU15 / 1FPU0 FPU1
Zen 212 / 0.5FPU0 FPU15 / 0.5FPU0 FPU112 / 0.5FPU0 FPU15 / 0.5FPU0 FPU1
Zen 311 / 0.5FP0 FP14 / 0.5FP0 FP111 / 0.5FP0 FP14 / 0.5FP0 FP1
Zen 411 / 0.5FP0 FP14 / 0.5FP0 FP111 / 0.5FP0 FP14 / 0.5FP0 FP14 / 1FP0 FP111 / 1FP0 FP1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.
VFMSUB231PS: element by elementResult single i comes from single i of xmm1, xmm2 and xmm3. Result singles 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.0123xmm1a0123xmm2b0123xmm3or m128c1110k1r0r1r3xmm1

Every single works alike: 4, 8 and 16 singles in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one single from memory stands for every element of the last source. The sources are drawn above the result, each element in its own column.

Result single i comes from single i of xmm1, xmm2 and xmm3. Result singles 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        zmm1.f32[i] = fmsub(b, c, a)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 15 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VFMSUB231PS xmm, xmm, xmm/m128 VFMSUB231PS ymm, ymm, ymm/m256
xmm, ymmexplicitread, write
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VFMSUB231PS xmm {k}{z}, xmm, xmm/m128/m32bcst VFMSUB231PS ymm {k}{z}, ymm, ymm/m256/m32bcst VFMSUB231PS zmm {k}{z}, zmm, zmm/m512/m32bcst, {er}
xmm, ymm, zmmexplicitread, write (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-2
EVEX forms
AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR
EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUB231PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fmsub_ps __m128 _mm_fmsub_ps(__m128 __A, __m128 __B, __m128 __C)

VFMSUB231PS xmm, xmm, xmm VEX.128 -mfmawhen __C is already in the destination register

_mm_mask3_fmsub_ps __m128 _mm_mask3_fmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U)

VFMSUB231PS xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_fmsub_ps __m128 _mm_maskz_fmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)

VFMSUB231PS xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vlwhen __C is already in the destination register

_mm256_fmsub_ps __m256 _mm256_fmsub_ps(__m256 __A, __m256 __B, __m256 __C)

VFMSUB231PS ymm, ymm, ymm VEX.256 -mfmawhen __C is already in the destination register

_mm256_mask3_fmsub_ps __m256 _mm256_mask3_fmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U)

VFMSUB231PS ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_fmsub_ps __m256 _mm256_maskz_fmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C)

VFMSUB231PS ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vlwhen __C is already in the destination register

_mm512_fmsub_ps __m512 _mm512_fmsub_ps(__m512 __A, __m512 __B, __m512 __C)

VFMSUB231PS zmm, zmm, zmm EVEX.512 -mavx512fwhen __C is already in the destination register

_mm512_fmsub_round_ps __m512 _mm512_fmsub_round_ps(__m512 A, __m512 B, __m512 C, const int R)

VFMSUB231PS zmm, zmm, zmm, {er} EVEX.512 -mavx512fwhen C is already in the destination register

_mm512_mask3_fmsub_ps __m512 _mm512_mask3_fmsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U)

VFMSUB231PS zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_mask3_fmsub_round_ps __m512 _mm512_mask3_fmsub_round_ps(__m512 A, __m512 B, __m512 C, __mmask16 U, const int R)

VFMSUB231PS zmm {k}, zmm, zmm, {er} EVEX.512 -mavx512f

_mm512_maskz_fmsub_ps __m512 _mm512_maskz_fmsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C)

VFMSUB231PS zmm {k}{z}, zmm, zmm EVEX.512 -mavx512fwhen __C is already in the destination register

_mm512_maskz_fmsub_round_ps __m512 _mm512_maskz_fmsub_round_ps(__mmask16 U, __m512 A, __m512 B, __m512 C, const int R)

VFMSUB231PS zmm {k}{z}, zmm, zmm, {er} EVEX.512 -mavx512fwhen C is already in the destination register

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
FMA

FMA + AVX
CPUID.01H:ECX[12] FMA
CPUID.01H:ECX[28] AVX

XED and Intel’s SDM differ: XED also asks for the AVX bit, CPUID.01H:ECX[28], besides FMA, CPUID.01H:ECX[12]. The opcode tables of revision 093 of Intel’s SDM name FMA alone for every VEX form, but its Volume 1 tells software to check for AVX first and then for FMA, so in effect the two agree.

Sources: Intel XED v2026.08.23, datafiles/hswavx/cpuid.xed.txt; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026), VFMADD132PD/VFMADD213PD/VFMADD231PD and the other FMA instructions: the opcode tables, from page 5-207; Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026), section 14.5.3, Detection of FMA, page 14-24.

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More FMA instructions

All 60 FMA instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-269 (VFMSUB132PS/VFMSUB213PS/VFMSUB231PS)
  6. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  7. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.