VFMSUBADD132PD

VFMSUBADD132PD computes op1 × op3 ± op2 for each double, rounded once: the even elements add op2 and the odd ones subtract it. It is the double form of VFMSUBADD132PS, whose page works through a product with a complex conjugate, and VFMSUBADD231PD is the 231 form. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, a multiplier of one double broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

In our builds#

At -O2 over double arrays, GCC 14 uses this form for three loops: a[i] * conj(b[i]) over double complex with -ffast-math, after VPERMILPD and VMULPD; and, without it, w[i] = x[i] * y[i] + z[i] then w[i+1] = x[i+1] * y[i+1] - z[i+1], and the same with z itself as the destination. y[i] comes from memory. Clang 23 uses VFMADD and VFMSUB forms instead, and VFMSUBADD213PD from the intrinsic.

Recorded on Zen 5#

• In vfmsubadd132pd ymm4, ymm4, ymmword ptr [mem] under MXCSR 7F80H (toward zero), the most negative finite double × 2 - itself in element 3 returned that double, FFEFFFFFFFFFFFFFH, with no flag set: the product is not rounded on its own, so it cannot overflow.
• vfmsubadd132pd zmm24{k3}, zmm3, zmm3, {rz-sae} computes x × x ± x. For x = 10^-300 in the odd element 3 it returned 81A56E1FC2F8F358H, the double just above -x: rounding toward zero drops the tiny product. For x = 1 + 2^-12 in element 7 it returned 2^-12 + 2^-24 exactly, 3F30010000000000H.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        if i % 2 == 0:
            zmm1.f64[i] = fmadd(a, c, b)
        else:
            zmm1.f64[i] = fmsub(a, c, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD132PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADD231SD
• VFMADD231SS
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD

All 60 FMA instructions

More AVX10.1 instructions

• VFMADDSUB231PH
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD

All 686 AVX10.1 instructions