VFMSUBADD132PH

VFMSUBADD132PH computes op1 × op3 ± op2 for each half-precision element and rounds once: the even elements (0, 2, 4 …) add op2 and the odd ones subtract it, the alternation the other way from VFMADDSUB132PH. The destination and the operand that may come from memory, or be broadcast from one half, are the factors, and the result goes over op1. VFMSUBADD231PS explains the family for singles and its use for a product with a conjugate, and VFMADD132PH covers the FP16 FMAs and what a merge mask keeps in each order. The opcode is 97h with the 66 prefix in EVEX map 6, the byte of VFMSUBADD132PS in map 0F38. Rounding follows MXCSR.RC, or {er} on the 512-bit register form, and DAZ and FTZ are ignored (Intel’s optimization manual, Section 18.5.4).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, without -ffast-math, GCC 14 fuses a loop that alternates by hand over global _Float16 arrays, r[i] = a[i] * b[i] + c[i] then r[i+1] = a[i+1] * b[i+1] - c[i+1], into VFMSUBADD132PH on zmm registers with b[i] read from memory; Clang 23 fuses it into VFMSUBADD213PH on ymm registers. For floats Clang does not: VFMSUBADD132PS’s page shows it negating every other c[i] and using plain FMAs.

_mm512_fmsubadd_ph(a, b, c) on three registers is VFMSUBADD132PH in GCC and VFMSUBADD213PH in Clang; with all three loaded from arrays, GCC keeps the 132 order and reads the second in place, while Clang reads the third.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMSUBADD132PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        if i % 2 == 0:
            zmm1.f16[i] = fmadd(a, c, b)
        else:
            zmm1.f16[i] = fmsub(a, c, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD132PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH

All 686 AVX10.1 instructions