VFMSUBADD132PS

VFMSUBADD132PS computes op1 × op3 ± op2 for each single, rounded once: the even elements add op2 and the odd ones subtract it. VFMSUBADD231PS covers the family and its mirror, and VFMADD132PS the operand roles of the 132 form, where the destination and the operand that may come from memory are the factors. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, a multiplier of one single broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

In our builds#

GCC 14 at -O2 with -ffast-math compiles a loop of a[i] * conjf(b[i]) over float complex arrays, (p + qi)(c - di), to this form: the destination holds a’s (p, q) pairs, op2 the products (qd, pd) from VMULPS, and op3 each (c, c), so the result is (pc + qd, qc - pd). Without -ffast-math, a loop that alternates by hand, r[i] = a[i] * b[i] + c[i] then r[i+1] = a[i+1] * b[i+1] - c[i+1], also becomes VFMSUBADD132PS, with b[i] from memory. Clang 23 splits the complex parts and uses VFMADD and VFMSUB on them, and in the second loop negates every other c[i] and uses VFMADD; it reaches the alternating instruction only from the intrinsic _mm256_fmsubadd_ps, as VFMSUBADD213PS.

Recorded on Zen 5#

• vfmsubadd132ps xmm4, xmm4, xmm4 computes x × x ± x. Under MXCSR 3FC0H (round down, DAZ), x = 1 gave 2 in element 0, x = -2.5 gave 6.25 + 2.5 = 8.75 in element 3, and x = 0.1 gave BDB851ECH, -0.0900000036, in element 1, rounded down.
• Under 5FC0H (round up), {evex} vfmsubadd132ps xmm1, xmm2, xmm3 turned (10^-30)^2 + 0 into the smallest denormal, 00000001H, and 1 × 2^-24 + 1 into 3F800001H, the single after 1, setting UE and PE.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        if i % 2 == 0:
            zmm1.f32[i] = fmadd(a, c, b)
        else:
            zmm1.f32[i] = fmsub(a, c, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD132PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADD231SS
• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB132PD
• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS

All 686 AVX10.1 instructions