VFMSUBADD213PD

VFMSUBADD213PD computes op2 × op1 ± op3 for each double, rounded once: the even elements add op3, the operand that may come from memory, and the odd ones subtract it. It is the double form of VFMSUBADD213PS; VFMSUBADD231PD covers the family’s doubles and VFMADD213PS the operand roles of the 213 form. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, an addend of one double broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

In our builds#

At -O2 over double arrays, with k a double parameter, GCC 14 compiles w[i] = x[i] * k + z[i] then w[i+1] = x[i+1] * k - z[i+1] to VFMSUBADD213PD with z[i] from memory, on ymm registers for -march=x86-64-v3 and zmm for -v4; Clang 23 negates every other z[i] with VXORPD and uses VFMADD231PD. The intrinsic _mm256_fmsubadd_pd with all three operands loaded from arrays becomes VFMSUBADD213PD in Clang, with the third from memory, and VFMSUBADD132PD in GCC.

FTZ on Zen 5#

The same product, 2^-1022 × 0.5, ran under two MXCSR settings. vfmsubadd213pd zmm14{k4}, zmm8, zmm29, {rd-sae}, MXCSR at 6600H with FTZ clear, added 2^-1074 in element 0 and returned the denormal 0008000000000001H exactly. vfmsubadd213pd zmm7{k3}, zmm12, qword bcst [mem] under FFC0H (toward zero, FTZ, DAZ) subtracted -0 in element 1 and returned +0, flushing the tiny result and setting UE and PE.

In the {rd-sae} case, 10^300 × 10^300 + (-10^300) in element 6 gave the largest finite double, 7FEFFFFFFFFFFFFFH: rounding down stops a positive overflow there, and MXCSR kept its flags clear.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        if i % 2 == 0:
            zmm1.f64[i] = fmadd(b, a, c)
        else:
            zmm1.f64[i] = fmsub(b, a, c)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD213PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADDSUB132PD
• VFMADDSUB132PS
• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB132PH
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD

All 686 AVX10.1 instructions