VFMSUBADD213PH

VFMSUBADD213PH computes op2 × op1 ± op3 for each half-precision element and rounds once: the even elements add op3, the operand that may come from memory or be broadcast from one half, and the odd ones subtract it, the result going over op1. VFMSUBADD132PH covers the FP16 forms, VFMADDSUB213PH is the mirror, and VFMSUBADD213PS the single-precision form. The opcode is A7h with the 66 prefix in EVEX map 6; rounding follows MXCSR.RC, or {er} on the 512-bit register form, and denormals are kept whatever DAZ and FTZ say, as VADDPH explains.

A product with a conjugate#

With the real part in the even element, (p + qi)(c - di) = (pc + qd) + (qc - pd)i adds in the even element and subtracts in the odd one. At -O2 with -march=x86-64-v4 -mavx512fp16 -ffast-math, Clang 23 computes a * ~b on two _Complex _Float16 values, ~ being the conjugate, with VMULPH and VFMSUBADD213PH: the multiplication gives (dq, dp) from d broadcast and a’s swapped pair, and VFMSUBADD213PH multiplies a by c broadcast and adds or subtracts that product. GCC 14 flips the sign of d and uses scalar FMAs, as VFCMULCSH’s page shows. In each step the result is rounded to FP16, which Intel’s optimization manual also says of the hardware’s complex multiply (Section 18.4.3).

In our builds#

Clang also uses VFMSUBADD213PH for a loop alternating by hand, r[i] = a[i] * b[i] + c[i] then r[i+1] = a[i+1] * b[i+1] - c[i+1], on ymm registers with c read from memory, and for _mm512_fmsubadd_ph(a, b, c) on three registers; GCC 14 takes the 132 order for both. With only the third operand in memory, both compilers use VFMSUBADD213PH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMSUBADD213PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        if i % 2 == 0:
            zmm1.f16[i] = fmadd(b, a, c)
        else:
            zmm1.f16[i] = fmsub(b, a, c)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD213PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH

All 686 AVX10.1 instructions