VFMSUBADD231PD

VFMSUBADD231PD computes op2 × op3 ± op1 for each double, rounded once: the even elements add the destination’s old value and the odd ones subtract it. It is the double form of VFMSUBADD231PS, which explains where the alternation fits, and the mirror of VFMADDSUB231PD. VFMADD231PS explains the three digits and what the EVEX forms add.

In our builds#

The 231 form keeps the running value in a register. A loop of s = _mm256_fmsubadd_pd(x, y, s), x and y loaded from arrays, becomes VFMSUBADD231PD in GCC 14 and Clang 23 at -O2, with y from memory. A product with a complex conjugate, a[i] * conj(b[i]) over double complex, takes VFMSUBADD132PD in GCC instead.

Recorded on Zen 5#

• In vfmsubadd231pd ymm24{k3}{z}, ymm3, ymm3 under MXCSR BF80H (round down, FTZ), 1 × 1 + (-1) in element 0 and 1 × 1 - 1 in element 1 both gave -0, the sign of an exact zero sum when rounding down; 2 × 2 - (-largest double) in element 3 gave the largest double and set only PE. Element 2, masked off, became zero.
• In vfmsubadd231pd ymm1, ymm2, ymmword ptr [mem] under 7F80H (toward zero), 2^-1022 × 0.5 - 2^-1074 in element 1 returned the denormal 0007FFFFFFFFFFFFH exactly, while 2^-1074 × 0.5 + (-0) in element 0, half the smallest denormal, became +0 and set UE and PE.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        if i % 2 == 0:
            zmm1.f64[i] = fmadd(b, c, a)
        else:
            zmm1.f64[i] = fmsub(b, c, a)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD231PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADDSUB213PD
• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB132SH
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD

All 686 AVX10.1 instructions