VFMSUBADD231PS

VFMSUBADD231PS computes op2 × op3 ± op1 for each single, rounded once, with the sign alternating the other way from VFMADDSUB231PS: the even elements (0, 2, 4 …) add the destination’s old value and the odd ones subtract it. VFMADD231PS covers what the family shares: the three-digit names, the single rounding, masking, broadcast and {er} in the EVEX forms.

A product with a conjugate#

With a complex number stored as its real part followed by its imaginary part, a × conj(b) = (p + qi)(c - di) = (pc + qd) + (qc - pd)i: the real part adds in the even element and the imaginary part subtracts in the odd one. In our builds at -O2 with -ffast-math, GCC 14 compiles a loop of a[i] * conjf(b[i]) to VPERMILPS, VMULPS and then VFMSUBADD132PS, on ymm registers for -march=x86-64-v3 and zmm for -v4; Clang 23 separates the real and imaginary parts and uses VFMADD231PS and VFMSUB231PS on them.

The 231 form appears when the running value stays in a register: a loop of s = _mm256_fmsubadd_ps(x, y, s), x and y loaded from arrays, becomes VFMSUBADD231PS in both compilers, with y from memory.

Both directions on Zen 5#

Two recorded cases ran the same inputs under opposite roundings: vfmsubadd231ps xmm0, xmm13, xmm9 under MXCSR 3FC0H (round down, DAZ) and {evex} vfmsubadd231ps xmm0, xmm31, xmm16 under 5FC0H (round up, DAZ).

• Element 1, odd: 3 × 0.1 - (-0.3) returned 3F199999H (0.599999964) and 3F19999AH (0.600000024), the singles on either side of the exact value.
• Element 3, odd: 2 × -2.5 - 4 gave -9 in both, where an even element would have added and given -1.
• Element 0, even: infinity × 1 plus minus infinity gave the default NaN FFC00000H and set IE.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1, as for VFMADD231PS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        if i % 2 == 0:
            zmm1.f32[i] = fmadd(b, c, a)
        else:
            zmm1.f32[i] = fmsub(b, c, a)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBADD231PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADDSUB213PS
• VFMADDSUB231PD
• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB213PD
• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS

All 686 AVX10.1 instructions