VFMSUBPS instruction (FMA4)

Forms

Every encoding of VFMSUBPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFMSUBPS xmm, xmm, m128, xmm` VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq	`VEX.128.66.0F3A.W0 6C /r /is4`	FMA4
`VFMSUBPS xmm, xmm, xmm, xmm` VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F3A.W0 6C /r /is4` `VEX.128.66.0F3A.W1 6C /r /is4`	FMA4
`VFMSUBPS xmm, xmm, xmm, m128` VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F3A.W1 6C /r /is4`	FMA4
`VFMSUBPS ymm, ymm, m256, ymm` VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq	`VEX.256.66.0F3A.W0 6C /r /is4`	FMA4
`VFMSUBPS ymm, ymm, ymm, ymm` VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F3A.W0 6C /r /is4` `VEX.256.66.0F3A.W1 6C /r /is4`	FMA4
`VFMSUBPS ymm, ymm, ymm, m256` VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F3A.W1 6C /r /is4`	FMA4

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Every single works alike: 4 and 8 singles in the xmm and ymm forms. The sources are drawn above the result, each element in its own column.

Result single i comes from single i of xmm2, xmm3 and xmm4. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 16 & 1:
    fault(UD)  # CPUID: no FMA4
for i in range(VL // 32):
    a = ymm2.f32[i]
    b = src3.f32[i]
    c = src4.f32[i]
    ymm1.f32[i] = fmsub(a, b, c)
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases. Its cases ran where CPUID reported no FMA4, and every one raised an exception. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFMSUBPS xmm, xmm, xmm/m128, xmm` `VFMSUBPS ymm, ymm, ymm/m256, ymm`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`xmm, ymm`	explicit	read
`VFMSUBPS xmm, xmm, xmm, m128` `VFMSUBPS ymm, ymm, ymm, m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm, ymm`	explicit	read
`m128/256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMSUBPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_msub_ps` `__m128 _mm_msub_ps(__m128 __A, __m128 __B, __m128 __C)`	`VFMSUBPS xmm, xmm, xmm, xmm` VEX.128 -mfma4
`_mm256_msub_ps` `__m256 _mm256_msub_ps(__m256 __A, __m256 __B, __m256 __C)`	`VFMSUBPS ymm, ymm, ymm, ymm` VEX.256 -mfma4

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`FMA4` FMA4	FMA4 `CPUID.80000001H:ECX[16]` FMA4	Bulldozer, Piledriver

VFMSUBPS