Instruction
VFMULCPH
Multiplies packed complex numbers, each a pair of half-precision values.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VFMULCPH xmm {k}{z}, xmm, xmm
VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | EVEX.128.F3.MAP6.W0 D6 /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VFMULCPH xmm {k}{z}, xmm, m128/m32bcst
VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | EVEX.128.F3.MAP6.W0 D6 /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VFMULCPH ymm {k}{z}, ymm, ymm
VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 | EVEX.256.F3.MAP6.W0 D6 /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VFMULCPH ymm {k}{z}, ymm, m256/m32bcst
VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 | EVEX.256.F3.MAP6.W0 D6 /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VFMULCPH zmm {k}{z}, zmm, zmm, {er}
VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 | EVEX.512.F3.MAP6.W0 D6 /r | AVX10.1 or AVX512_FP16 |
VFMULCPH zmm {k}{z}, zmm, m512/m32bcst
VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 | EVEX.512.F3.MAP6.W0 D6 /r | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VFMULCPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_fmul_pch
__m128h _mm_fmul_pch(__m128h __A, __m128h __B) |
|
_mm_mul_pch
__m128h _mm_mul_pch(__m128h A, __m128h B) |
|
_mm_mask_fmul_pch
__m128h _mm_mask_fmul_pch(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) |
|
_mm_mask_mul_pch
__m128h _mm_mask_mul_pch(__m128h W, __mmask8 U, __m128h A, __m128h B) |
|
_mm_maskz_fmul_pch
__m128h _mm_maskz_fmul_pch(__mmask8 __U, __m128h __A, __m128h __B) |
|
_mm_maskz_mul_pch
__m128h _mm_maskz_mul_pch(__mmask8 U, __m128h A, __m128h B) |
|
_mm256_fmul_pch
__m256h _mm256_fmul_pch(__m256h __A, __m256h __B) |
|
_mm256_mul_pch
__m256h _mm256_mul_pch(__m256h A, __m256h B) |
|
_mm256_mask_fmul_pch
__m256h _mm256_mask_fmul_pch(__m256h __W, __mmask8 __U, __m256h __A, __m256h __B) |
|
_mm256_mask_mul_pch
__m256h _mm256_mask_mul_pch(__m256h W, __mmask8 U, __m256h A, __m256h B) |
|
_mm256_maskz_fmul_pch
__m256h _mm256_maskz_fmul_pch(__mmask8 __U, __m256h __A, __m256h __B) |
|
_mm256_maskz_mul_pch
__m256h _mm256_maskz_mul_pch(__mmask8 U, __m256h A, __m256h B) |
|
_mm512_fmul_pch
__m512h _mm512_fmul_pch(__m512h __A, __m512h __B) |
|
_mm512_fmul_round_pch
__m512h _mm512_fmul_round_pch(__m512h A, __m512h B, const int R) |
|
_mm512_mul_pch
__m512h _mm512_mul_pch(__m512h A, __m512h B) |
|
_mm512_mul_round_pch
__m512h _mm512_mul_round_pch(__m512h A, __m512h B, const int R) |
|
_mm512_mask_fmul_pch
__m512h _mm512_mask_fmul_pch(__m512h __W, __mmask16 __U, __m512h __A, __m512h __B) |
|
_mm512_mask_fmul_round_pch
__m512h _mm512_mask_fmul_round_pch(__m512h W, __mmask16 U, __m512h A, __m512h B, const int R) |
|
_mm512_mask_mul_pch
__m512h _mm512_mask_mul_pch(__m512h W, __mmask16 U, __m512h A, __m512h B) |
|
_mm512_mask_mul_round_pch
__m512h _mm512_mask_mul_round_pch(__m512h W, __mmask16 U, __m512h A, __m512h B, const int R) |
|
_mm512_maskz_fmul_pch
__m512h _mm512_maskz_fmul_pch(__mmask16 __U, __m512h __A, __m512h __B) |
|
_mm512_maskz_fmul_round_pch
__m512h _mm512_maskz_fmul_round_pch(__mmask16 U, __m512h A, __m512h B, const int R) |
|
_mm512_maskz_mul_pch
__m512h _mm512_maskz_mul_pch(__mmask16 U, __m512h A, __m512h B) |
|
_mm512_maskz_mul_round_pch
__m512h _mm512_maskz_mul_round_pch(__mmask16 U, __m512h A, __m512h B, const int R) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_128 | AVX10.1 or AVX512_FP16 + AVX512VL | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_FP16_256 | AVX10.1 or AVX512_FP16 + AVX512VL | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_FP16_512 | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VFMSUB213PH
- VFMSUB213PS
- VFMSUB213SD
- VFMSUB213SH
- VFMSUB213SS
- VFMSUB231PD
- VFMSUB231PH
- VFMSUB231PS
- VFMSUB231SD
- VFMSUB231SH
- VFMSUB231SS
- VFMSUBADD132PD
- VFMSUBADD132PH
- VFMSUBADD132PS
- VFMSUBADD213PD
- VFMSUBADD213PH
- VFMSUBADD213PS
- VFMSUBADD231PD
- VFMSUBADD231PH
- VFMSUBADD231PS
- VFMULCSH
- VFNMADD132PD
- VFNMADD132PH
- VFNMADD132PS
- VFNMADD132SD
- VFNMADD132SH
- VFNMADD132SS
- VFNMADD213PD
- VFNMADD213PH
- VFNMADD213PS
- VFNMADD213SD
- VFNMADD213SH
- VFNMADD213SS
- VFNMADD231PD
- VFNMADD231PH
- VFNMADD231PS
- VFNMADD231SD
- VFNMADD231SH
- VFNMADD231SS
- VFNMSUB132PD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.