VFMULCPH

VFMULCPH multiplies complex numbers stored as pairs of halves, the real part in the even element and the imaginary part in the odd one above it: 16 products per zmm register. For a + bi times c + di it computes ac - bd and ad + bc. It is one of eight complex instructions of AVX512-FP16: VFCMULCPH multiplies by the complex conjugate of the second source, VFMADDCPH and VFCMADDCPH add the product to the destination, and VFMULCSH and the other SH forms handle the lowest pair only. VADDPH covers the format and the CPUID bits. Complex sums need no instruction of their own.

Pairs as elements#

Everything that is per element elsewhere is per pair here: one mask bit covers both halves of a product, and a broadcast reads one 32-bit pair from memory ({1to16}). The encoding is D6h with the F3 prefix in EVEX map 6; the conjugating form has F2. The destination may be neither source register, or the instruction raises #UD, so compilers always compute into a third register.

The product is not correctly rounded. Intel’s optimization manual explains that the hardware runs it as a multiply followed by a fused multiply-add for each part, and rounds to FP16 after each step (Sections 18.4.3 and 18.5.3). Intel’s entry adds that it runs as if every MXCSR exception were masked, so it never faults on a floating-point exception, though it still sets the status flags.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 keep z[i] = x[i] * y[i] over _Complex _Float16 arrays scalar: they compute each product with VMULSH and its relatives and call the library’s __mulhc3 only for a NaN result. With -ffast-math or -fcx-limited-range, GCC vectorizes the loop to VFMULCPH on zmm registers with one factor from memory; Clang splits the real and imaginary parts and multiplies them on xmm registers: with -ffast-math by VMULPH followed by VFMSUB231PH and VFMADD231PH, much as the hardware does, and with -fcx-limited-range by four VMULPH, a VSUBPH and a VADDPH. _mm512_fmul_pch(a, b) gives VFMULCPH in both, followed by a move out of the third register; for a pair broadcast from memory, Clang folds the load into {1to16} and GCC loads it with VBROADCASTSS first.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMULCPH.

In the optimization guide

What the optimization guide says about VFMULCPH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.
• Vectors, AVX-512 and AMX: AVX-512 FP16 adds and multiplies 32 half-precision values per 512-bit register with a latency of four cycles; division and square root take about 31. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if zmm1.number == zmm2.number:
    fault(UD)
if not src3.is_memory:
    if zmm1.number == src3.number:
        fault(UD)
for i in range(VL // 32):
    if k1[i]:
        ar = zmm2.f16[2 * i]
        ai = zmm2.f16[2 * i + 1]
        br = src3.f16[2 * i]
        bi = src3.f16[2 * i + 1]
        x = mul(ar, br)
        y = mul(ai, br)
        x = fnmadd(ai, bi, x)
        y = fmadd(ar, bi, y)
        zmm1.d[i] = y << 16 | x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# (ar + ai*i)(br + bi*i) = x + y*i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMULCPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUB213PH
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD

All 686 AVX10.1 instructions