VFMULCSH

VFMULCSH multiplies the lowest complex number of its first source, the halves in bits 15:0 (real) and 31:16 (imaginary), by that of the second: for a + bi times c + di it writes ac - bd and ad + bc to the low 32 bits of the destination. Bits 127:32 come from the first source and the bits above 127 are cleared. It is the scalar form of VFMULCPH, whose page covers the pair layout, the rounding after each internal step and the exceptions, which set MXCSR’s flags but never fault; VFCMULCSH conjugates the second factor, and VADDPH covers the format and the CPUID bits.

A scalar of 32 bits#

The scalar here is a pair, so the write mask uses bit 0 for both halves and a memory operand is 32 bits, where the real scalar FP16 instructions such as VMULSH read 16. The encoding is D7h with the F3 prefix in EVEX map 6, one above the packed form’s D6h; it takes {er} between registers. As for the packed form, the destination register must differ from both sources, or the instruction raises #UD.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 emit VFMULCSH for the intrinsics _mm_fmul_sch and _mm_mul_sch, and _mm_fmul_round_sch with _MM_FROUND_TO_ZERO gives vfmulcsh xmm2, xmm0, xmm1, {rz-sae} followed by a move to XMM0, since the result may not overwrite the first source. A function multiplying two _Complex _Float16 values does not use it: by default both compilers compute it with scalar arithmetic and call the library’s __mulhc3 only for a NaN result, and with -ffast-math GCC computes the parts with VMULSH, VFMSUB132SH and VFMADD132SH, Clang with VMULPH and VFMADDSUB231PH on broadcast and swapped halves.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFMULCSH.

In the optimization guide

What the optimization guide says about VFMULCSH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if xmm1.number == xmm2.number:
    fault(UD)
if not src3.is_memory:
    if xmm1.number == src3.number:
        fault(UD)
if k1[0]:
    ar = xmm2.f16[0]
    ai = xmm2.f16[1]
    br = src3.f16[0]
    bi = src3.f16[1]
    x = mul(ar, br)
    y = mul(ai, br)
    x = fnmadd(ai, bi, x)
    y = fmadd(ar, bi, y)
    xmm1.d[0] = y << 16 | x
elif zeroing:
    xmm1.d[0] = 0
# else: xmm1.d[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# (ar + ai*i)(br + bi*i) = x + y*i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFMULCSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH

All 686 AVX10.1 instructions