Instruction
VFMULCSH
Multiplies the low complex numbers, each a pair of half-precision values.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VFMULCSH xmm {k}{z}, xmm, xmm, {er}
VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | EVEX.LIG.F3.MAP6.W0 D7 /r | AVX10.1 or AVX512_FP16 |
VFMULCSH xmm {k}{z}, xmm, m32
VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | EVEX.LIG.F3.MAP6.W0 D7 /r | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VFMULCSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_fmul_round_sch
__m128h _mm_fmul_round_sch(__m128h A, __m128h B, const int R) |
|
_mm_fmul_sch
__m128h _mm_fmul_sch(__m128h __A, __m128h __B) |
|
_mm_mul_round_sch
__m128h _mm_mul_round_sch(__m128h A, __m128h B, const int R) |
|
_mm_mul_sch
__m128h _mm_mul_sch(__m128h A, __m128h B) |
|
_mm_mask_fmul_round_sch
__m128h _mm_mask_fmul_round_sch(__m128h W, __mmask8 U, __m128h A, __m128h B, const int R) |
|
_mm_mask_fmul_sch
__m128h _mm_mask_fmul_sch(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) |
|
_mm_mask_mul_round_sch
__m128h _mm_mask_mul_round_sch(__m128h W, __mmask8 U, __m128h A, __m128h B, const int R) |
|
_mm_mask_mul_sch
__m128h _mm_mask_mul_sch(__m128h W, __mmask8 U, __m128h A, __m128h B) |
|
_mm_maskz_fmul_round_sch
__m128h _mm_maskz_fmul_round_sch(__mmask8 U, __m128h A, __m128h B, const int R) |
|
_mm_maskz_fmul_sch
__m128h _mm_maskz_fmul_sch(__mmask8 __U, __m128h __A, __m128h __B) |
|
_mm_maskz_mul_round_sch
__m128h _mm_maskz_mul_round_sch(__mmask8 U, __m128h A, __m128h B, const int R) |
|
_mm_maskz_mul_sch
__m128h _mm_maskz_mul_sch(__mmask8 U, __m128h A, __m128h B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_SCALAR | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VFMSUB213PS
- VFMSUB213SD
- VFMSUB213SH
- VFMSUB213SS
- VFMSUB231PD
- VFMSUB231PH
- VFMSUB231PS
- VFMSUB231SD
- VFMSUB231SH
- VFMSUB231SS
- VFMSUBADD132PD
- VFMSUBADD132PH
- VFMSUBADD132PS
- VFMSUBADD213PD
- VFMSUBADD213PH
- VFMSUBADD213PS
- VFMSUBADD231PD
- VFMSUBADD231PH
- VFMSUBADD231PS
- VFMULCPH
- VFNMADD132PD
- VFNMADD132PH
- VFNMADD132PS
- VFNMADD132SD
- VFNMADD132SH
- VFNMADD132SS
- VFNMADD213PD
- VFNMADD213PH
- VFNMADD213PS
- VFNMADD213SD
- VFNMADD213SH
- VFNMADD213SS
- VFNMADD231PD
- VFNMADD231PH
- VFNMADD231PS
- VFNMADD231SD
- VFNMADD231SH
- VFNMADD231SS
- VFNMSUB132PD
- VFNMSUB132PH
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.