VFNMADD132PH

VFNMADD132PH computes -(op1 × op3) + op2 for each half-precision element and rounds once, writing over op1: the product of the destination and the operand that may come from memory, or be broadcast from one half, is negated and the middle register added. It is the negated twin of VFMADD132PH, whose page covers the FP16 family and what a merge mask keeps in each order; VFNMADD213PH and VFNMADD231PH are the other orders, and VFNMADD132PS the single-precision form. The opcode is 9Ch with the 66 prefix in EVEX map 6. Rounding follows MXCSR.RC, or {er} on the 512-bit register form, and DAZ and FTZ are ignored (Intel’s optimization manual, Section 18.5.4).

GCC’s order#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles c[i] = d[i] - a[i] * b[i] and c[i] -= a[i] * b[i] over global _Float16 arrays to VFNMADD132PH on zmm registers, reading b[i] from memory; Clang 23 uses VFNMADD213PH on ymm registers with the addend from memory. _mm512_fnmadd_ph(a, b, c) on three registers splits the same way, and _mm512_mask_fnmadd_ph(a, k, b, c), which keeps a where the mask is clear, is VFNMADD132PH in both. A factor broadcast from memory also picks this order in GCC: _mm512_fnmadd_ph(a, _mm512_set1_ph(*p), _mm512_set1_ph(1.0f16)) reads *p with {1to32}.

Which negation folds#

Both compilers fold a negated factor, _mm512_fmadd_ph(-a, b, c), into the negated form, since -a × b is exactly -(a × b). Negating the result, -_mm512_fmadd_ph(a, b, c), stays a VFMADD followed by an XOR of the sign bits: it is not -(a × b) - c, which differs in the sign of a zero result.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMADD132PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fnmadd(a, c, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD132PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUB213SH
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD

All 686 AVX10.1 instructions