VFNMADD132PS

VFNMADD132PS computes -(op1 × op3) + op2 for each single, rounded once: the product of the destination and the operand that may come from memory is subtracted from the middle register. VFNMADD231PS covers the negated family, its uses and the signs of its NaNs, and VFMADD132PS the operand roles of the 132 form. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, a multiplier of one single broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

GCC’s choice#

In our builds at -O2 over fixed-size float arrays, with -march=x86-64-v3 (ymm) and -v4 (zmm), GCC 14 uses VFNMADD132PS for a[i] = d[i] - b[i] * c[i] and acc[i] -= b[i] * c[i], one factor from memory. For the polynomial 2 - (1 - (0.5 - 0.25 * t) * t) * t with t = b[i], it chains three VFNMADD132PS that each read b[i] from memory again, with the constants in registers. Clang 23 uses VFNMADD213PS for all three loops.

Rounding on Zen 5#

With one register for all three operands, vfnmadd132ps ymm4, ymm4, ymm4 computes x - x × x. Under MXCSR DF80H (round up, FTZ):

• for x = 10^-30 it returned x itself, 0DA24260H: the exact result lies just below x, and rounding up brings it back. The same values in vfnmadd132ps zmm24{k3}, zmm3, zmm3, {rz-sae}, rounding toward zero, gave 0DA2425FH, the single below x;
• for x = 10^30 it returned -3.40282347e38, the most negative finite single, not minus infinity: rounding up stops a negative overflow there. OE and PE were set.

In that {rz-sae} case, with MXCSR at 6600H and invalid unmasked, the element computing -(infinity × 0) + 0 got the default NaN FFC00000H without a fault, and MXCSR kept its flags clear.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        zmm1.f32[i] = fnmadd(a, c, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD132PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMADDSUB231PS
• VFMSUB132PD
• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PS

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH

All 686 AVX10.1 instructions