VFNMADD132SH

VFNMADD132SH computes -(op1 × op3) + op2 on the low halves and rounds once, writing over op1, a factor. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFNMADD132PH; VFNMADD213SH and VFNMADD231SH are the other operand orders, VFMADD132SH explains what the scalar FMAs keep, and VFNMADD132SS is the single-precision form. The encoding is 9Dh with the 66 prefix in EVEX map 6; it takes {er} between registers and reads two bytes from memory.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles z - x * y, __builtin_fmaf16(-x, y, z) and _mm_fnmadd_sh(a, b, c) on _Float16 values to VFNMADD132SH, Clang 23 to VFNMADD213SH; with a factor from memory, z - x * a[5], both use VFNMADD132SH. GCC also keeps r[i] -= p[i] * q[i] through pointer parameters scalar at -O2 with VFNMADD132SH reading q[i] in place, because the arrays may overlap: with restrict on the parameters a constant 1,024 elements run VFNMADD132PH on zmm registers, while a count known only at run time stays scalar either way. At -O3 GCC checks for overlap at run time and vectorizes.

A running sum of negated products, s -= a[i] * b[i] over _Float16 arrays, shows how differently the two keep C’s order of operations. Clang compiles it to a chain of scalar FMAs, a VFNMADD231SH and then VFNMADD132SH, each reading one half from memory and each depending on the one before. GCC fuses nothing there: it multiplies 32 pairs at a time with VMULPH and subtracts the products one by one with VSUBSH. Only -ffast-math lets GCC accumulate with VFNMADD231PH in vector registers.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMADD132SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fnmadd(a, c, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD132SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUB231PH
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD

All 686 AVX10.1 instructions