VFNMADD213PD

VFNMADD213PD computes -(op2 × op1) + op3 for each double, rounded once: the destination is a factor and the addend is the operand that may come from memory, which suits c - x × y with c in memory. It is the double form of VFNMADD213PS; VFNMADD231PS covers the negated family. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, an addend of one double broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

In our builds#

At -O2 over double arrays, Clang 23 uses VFNMADD213PD on ymm registers, with -march=x86-64-v3 and -v4, for w[i] = z[i] - x[i] * y[i] and w[i] -= x[i] * y[i], the addend from memory, where GCC 14 takes VFNMADD132PD. For w[i] = z[i] - x[i] * k, k in a register, both compilers use VFNMADD213PD with z[i] from memory. In the polynomial 2 - (1 - (0.5 - 0.25 * t) * t) * t, Clang loads t = x[i] once: a VFMADD213PD with the constant -0.25, then two VFNMADD213PD.

Recorded on Zen 5#

• -(3 × 0.1) + (-0.3) ran in two rounding directions: vfnmadd213pd xmm1, xmm2, xmmword ptr [mem] under MXCSR 7F80H (toward zero) gave BFE3333333333333H, and vfnmadd213pd ymm0{k2}{z}, ymm31, ymm16 under BF80H (round down) BFE3333333333334H, one double further from zero.
• Under 3FC0H (round down, DAZ), vfnmadd213pd xmm1, xmm2, xmm3 computed -(2^-1022 × 0.5) + 2^-1074 as 8008000000000000H, exactly -2^-1023: DAZ counted the denormal addend as zero, while the denormal result stayed, FTZ being clear.
• Under DF80H (round up, FTZ), vfnmadd213pd ymm1, ymm2, ymm3 gave the most negative finite double for -(largest × 2) + (-largest), where rounding up stops a negative overflow.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        zmm1.f64[i] = fnmadd(b, a, c)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD213PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SS

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB231SD
• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS

All 686 AVX10.1 instructions