VFNMADD213PH

VFNMADD213PH computes -(op2 × op1) + op3 for each half-precision element, rounded once and written over op1: the product is negated, not the sum, the destination is a factor, and the addend is the operand that may come from memory or be broadcast from one half. It is the negated twin of VFMADD213PH, whose page covers the 213 order; VFMADD132PH covers the FP16 family and its masking, and VFNMADD213PS the single-precision form, with the signs of zero results. Rounding follows MXCSR.RC, or {er} on the 512-bit register form, and denormals are kept whatever DAZ and FTZ say, as VADDPH explains.

c minus a product#

d[i] - a[i] * b[i] over _Float16 arrays is the case this order fits, with d[i] read from memory as the addend. At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 compiles it, and c[i] -= a[i] * b[i] too, to VFNMADD213PH on ymm registers; GCC 14 uses VFNMADD132PH on zmm registers with b[i] from memory instead. On one value, z - x * y is VFNMADD213SH in Clang and VFNMADD132SH in GCC, and _mm512_fnmadd_ph on three registers follows the same split. The rounding is the same either way: the exact value of z - x × y, rounded once, which two instructions would round twice.

A half has only 11 significant bits, so that single rounding matters more than for singles. When x × y is close to z, the difference cancels most of the bits, and VMULPH followed by VSUBPH keeps the error of the rounded product, which can be as large as the result itself; the fused form gives the difference correctly rounded.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMADD213PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fnmadd(b, a, c)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD213PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUB231SH
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD

All 686 AVX10.1 instructions