VFNMADD213PS

VFNMADD213PS computes -(op2 × op1) + op3 for each single, rounded once: the destination is a factor and the addend is the operand that may come from memory, which suits c - x × y with c in memory and chains in which each result is multiplied again. VFNMADD231PS covers the negated family, and VFMADD213PS the operand roles of the 213 form. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, an addend of one single broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

Clang’s choice#

In our builds at -O2 over fixed-size float arrays, with -march=x86-64-v3 and -v4, Clang 23 uses VFNMADD213PS on ymm registers for a[i] = d[i] - b[i] * c[i] and acc[i] -= b[i] * c[i], with d[i] or acc[i] from memory, where GCC 14 takes VFNMADD132PS. For a[i] = c[i] - b[i] * k, k in a register, both compilers use VFNMADD213PS with c[i] from memory. In the polynomial 2 - (1 - (0.5 - 0.25 * t) * t) * t, Clang loads t = b[i] once and keeps the rest in registers: a VFMADD213PS with the constant -0.25 for the innermost step, then two VFNMADD213PS.

Signs on Zen 5#

vfnmadd213ps xmm4, xmm4, xmm4 computes x - x × x. Under MXCSR 3FC0H (round down, DAZ), x = +0 gave -0: the negated product, -0, plus +0 is an exact zero from opposite signs, and rounding down makes such a zero negative; x = -0 gave -0 as well, the sum of two negative zeros. In vfnmadd213ps ymm12, ymm6, ymm6 under DF80H (round up, FTZ), -(-0 × 0) + -0 gave +0, and -(-10^30 × 10^30) - 10^30 overflowed to plus infinity, setting OE and PE; a negative overflow rounded up stops at the most negative finite single instead, as VFNMADD132PS’s page shows.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        zmm1.f32[i] = fnmadd(b, a, c)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD213PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SS

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH

All 686 AVX10.1 instructions