VFNMADD213SH

VFNMADD213SH computes -(op2 × op1) + op3 on the low halves and rounds once: op1 is a factor and is overwritten, and op3, the operand that may come from memory, is the addend. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFNMADD213PH; VFNMADD132SH and VFNMADD231SH are the other operand orders, VFMADD213SH the same order without the negation, and VFNMADD213SS the single-precision form. The encoding is ADh with the 66 prefix in EVEX map 6; it takes {er} between registers and reads two bytes from memory.

One minus a product#

1 - x × r measures how far r is from the reciprocal of x, the first step of a Newton correction. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile it on _Float16 values to one VFNMADD213SH with the constant 1.0 read from memory, and a[5] - x * y the same way. Intel’s optimization manual puts the FP16 reciprocal estimate within 0.5 ULP for 98% of inputs and 0.5625 ULP for the rest, and suggests the division only where IEEE behavior is required (Section 18.5.8.1).

A constant subtracted from a negated product also lands here: both compilers turn -(x * y) - 1 into VFNMADD213SH adding -1. A polynomial in Horner form with negated steps, -((-(x * 3) - 2) * x) - 1, gives GCC a chain of two VFNMADD213SH, each adding a coefficient from memory.

With all three operands in registers, Clang uses VFNMADD213SH for the expression z - x * y, for _mm_fnmadd_sh and for the masked _mm_mask_fnmadd_sh and _mm_maskz_fnmadd_sh; GCC picks VFNMADD132SH for all of these.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMADD213SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fnmadd(b, a, c)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD213SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUBADD132PH
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD

All 686 AVX10.1 instructions