VFNMADD231PH

VFNMADD231PH computes op1 - op2 × op3 for each half-precision element, rounded once: the destination is the addend, so it subtracts products from what a register holds, acc -= x × y, with one factor from memory or broadcast from a single half. VFNMADD231PS explains the negated family for singles, with a table of the four sign combinations, and VFMADD132PH covers the FP16 forms and what a merge mask keeps; VADDPH explains the format and the CPUID bits.

Residuals#

r - x × y in one rounding is what numerical code uses to measure an error: a - q × b says how far a quotient q is off, and 1 - x × r how far a reciprocal r is. Intel’s optimization manual finds the FP16 approximations good enough to need no Newton step: VRCPPH and VRSQRTPH are within 0.5 ULP for 98% of inputs and 0.5625 ULP for the rest, and a division done as a multiplication by the reciprocal stays within about 1.5 ULP except for divisors near either end of the range (Sections 18.5.8.1 and 18.5.8.2). A residual computed by this instruction tells a program that needs the correctly rounded quotient when to correct it.

In our builds#

The 231 order appears when the addend stays in its register. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile _mm512_mask3_fnmadd_ph(a, b, c, k), which must keep c where the mask is clear, to VFNMADD231PH with c as destination. The loop c[i] -= a[i] * b[i] over _Float16 arrays, where the addend comes from memory, takes the other orders instead: VFNMADD213PH in Clang and VFNMADD132PH in GCC.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMADD231PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fnmadd(b, c, a)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD231PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMSUBADD213PH
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD

All 686 AVX10.1 instructions