VFNMADD231PS

VFNMADD231PS computes op1 - op2 × op3 for each single, rounded once: the product is negated, not the sum. It is the subtracting twin of VFMADD231PS, whose page explains the three digits, the masking and the {er} rounding of the EVEX forms. The four FMA families differ only in two signs:

What it is for#

z - x × y in one rounding is the residual of numerical code: the error of a quotient, a - q × b, or the step of Newton’s method for a reciprocal, 1 - x × r, both exact as long as the result is representable. In our builds at -O2 with -march=x86-64-v3, the loop acc[i] -= x[i] * y[i] over floats becomes VFNMADD213PS in Clang 23, with acc[i] from memory, and VFNMADD132PS in GCC 14. The 231 form appears when the sum stays in a register: with -ffast-math, GCC compiles s -= x[i] * y[i] to VFNMADD231PS on zmm registers for -march=x86-64-v4, while Clang multiplies one pair with VMULPS, folds the next in with VFNMSUB231PS, -(x × y) - p, and adds that to its sums.

Signs on Zen 5#

The negation applies to numbers, not to NaNs, as Intel’s table of FMA results lists (Volume 1, Table 14-17). In the recorded cases:

• the quiet NaN 7FC12345H as a factor came back as 7FC12345H, its sign bit still clear, in preference to the addend FFC00005H;
• infinity × 0 with the addend 7FC12345H returned that addend, not the default NaN FFC00000H, which the same product gave with the addend 1;
• under {rz-sae}, -(10^-30 × 10^-30) + 0 gave -0: the exact result is a tiny negative number, and rounding it toward zero keeps its sign.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        zmm1.f32[i] = fnmadd(b, c, a)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD231PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SS

All 60 FMA instructions

More AVX10.1 instructions

• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PH
• VFMSUBADD231PS
• VFMULCPH
• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH

All 686 AVX10.1 instructions