VFNMADD231SH instruction (AVX10.1)

VFNMADD231SH computes op1 - op2 × op3 on the low halves and rounds once: the destination is the addend, so it subtracts a product from what a register holds, acc -= x × y. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFNMADD231PH, whose page explains residuals; VFNMADD132SH and VFNMADD213SH are the other operand orders, and VFNMADD231SS the single-precision form. The encoding is BDh with the 66 prefix in EVEX map 6; it takes {er} and reads two bytes when op3 is in memory.

Residuals in our builds

The 231 order fits when the value a product is taken from arrives first. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile a - q * b on three _Float16 arguments, with a already in XMM0, to vfnmadd231sh xmm0, xmm2, xmm1. A function that divides with VDIVSH, takes the remainder __builtin_fmaf16(-q, b, a) and adds r / b back does the same in both: VDIVSH, VFNMADD231SH, VDIVSH and VADDSH. The masked _mm_mask3_fnmadd_sh(a, b, c, k), which keeps c when bit 0 of the mask is clear, is VFNMADD231SH in both, with c as destination.

Clang also starts the chain of scalar FMAs for s -= a[i] * b[i] over _Float16 arrays with VFNMADD231SH, then continues with VFNMADD132SH as the next factor comes from memory; GCC multiplies with VMULPH and subtracts with VSUBSH instead.

Intel’s optimization manual counts the fused multiply-add among the FP16 operations that are correctly rounded, to 0.5 ULP when rounding to nearest (Section 18.5.3).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMADD231SH.

Forms

Every encoding of VFNMADD231SH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFNMADD231SH xmm {k}{z}, xmm, xmm, {er}` VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512	`EVEX.LIG.66.MAP6.W0 BD /r`	AVX10.1 or AVX512_FP16
`VFNMADD231SH xmm {k}{z}, xmm, m16` VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512	`EVEX.LIG.66.MAP6.W0 BD /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm {k}{z}, xmm, xmm, {er}`no mask, with {er}	`xmm {k}{z}, xmm, xmm, {er}`with a mask, zeroing	`xmm {k}{z}, xmm, m16`
Sapphire Rapids	5 / 0.5p01	6 / 0.5p01	12 / 0.5p01

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low half is computed; the other halves come from xmm1.

The write mask k1 applies to the low half: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result half 0 is computed from half 0 of xmm1, xmm2 and xmm3; halves 7 to 1 are those of xmm1. Result halves 7 to 0: a7, a6, a5, a4, a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fnmadd(b, c, a)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Not run on a processor: none of these processors has AVX512-FP16. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFNMADD231SH xmm {k}{z}, xmm, xmm/m16, {er}`
`xmm`	explicit	read, write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMADD231SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mask3_fnmadd_round_sh` `__m128h _mm_mask3_fnmadd_round_sh(__m128h W, __m128h X, __m128h Y, __mmask8 U, const int R)`	`VFNMADD231SH xmm {k}, xmm, xmm, {er}` EVEX.LIG -mavx512fp16
`_mm_mask3_fnmadd_sh` `__m128h _mm_mask3_fnmadd_sh(__m128h __W, __m128h __X, __m128h __Y, __mmask8 __U)`	`VFNMADD231SH xmm {k}, xmm, xmm` EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Residuals in our builds#