Instruction
VFNMSUB132BF16
Fused negated multiply-subtract of packed bfloat16 values: minus first operand times third, minus second, into the first.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VFNMSUB132BF16 xmm {k}{z}, xmm, xmm
VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 | EVEX.128.NP.MAP6.W0 9E /r | AVX10.2 |
VFNMSUB132BF16 xmm {k}{z}, xmm, m128/m16bcst
VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 | EVEX.128.NP.MAP6.W0 9E /r | AVX10.2 |
VFNMSUB132BF16 ymm {k}{z}, ymm, ymm
VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 | EVEX.256.NP.MAP6.W0 9E /r | AVX10.2 |
VFNMSUB132BF16 ymm {k}{z}, ymm, m256/m16bcst
VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 | EVEX.256.NP.MAP6.W0 9E /r | AVX10.2 |
VFNMSUB132BF16 zmm {k}{z}, zmm, zmm
VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 | EVEX.512.NP.MAP6.W0 9E /r | AVX10.2 |
VFNMSUB132BF16 zmm {k}{z}, zmm, m512/m16bcst
VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 | EVEX.512.NP.MAP6.W0 9E /r | AVX10.2 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VFNMSUB132BF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_fnmsub_pbh
__m128bh _mm_fnmsub_pbh(__m128bh __A, __m128bh __B, __m128bh __C) |
|
_mm_mask_fnmsub_pbh
__m128bh _mm_mask_fnmsub_pbh(__m128bh __A, __mmask8 __U, __m128bh __B, __m128bh __C) |
|
_mm_maskz_fnmsub_pbh
__m128bh _mm_maskz_fnmsub_pbh(__mmask8 __U, __m128bh __A, __m128bh __B, __m128bh __C) |
|
_mm256_fnmsub_pbh
__m256bh _mm256_fnmsub_pbh(__m256bh __A, __m256bh __B, __m256bh __C) |
|
_mm256_mask_fnmsub_pbh
__m256bh _mm256_mask_fnmsub_pbh(__m256bh __A, __mmask16 __U, __m256bh __B, __m256bh __C) |
|
_mm256_maskz_fnmsub_pbh
__m256bh _mm256_maskz_fnmsub_pbh(__mmask16 __U, __m256bh __A, __m256bh __B, __m256bh __C) |
|
_mm512_fnmsub_pbh
__m512bh _mm512_fnmsub_pbh(__m512bh __A, __m512bh __B, __m512bh __C) |
|
_mm512_mask_fnmsub_pbh
__m512bh _mm512_mask_fnmsub_pbh(__m512bh __A, __mmask32 __U, __m512bh __B, __m512bh __C) |
|
_mm512_maskz_fnmsub_pbh
__m512bh _mm512_maskz_fnmsub_pbh(__mmask32 __U, __m512bh __A, __m512bh __B, __m512bh __C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX10_2_BF16_128 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX10_2_BF16_256 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX10_2_BF16_512 | AVX10.2 | Nova Lake, Diamond Rapids |
More AVX10.2 instructions
- VCVTTPS2IBS
- VCVTTPS2IUBS
- VCVTTPS2QQS
- VCVTTPS2UDQS
- VCVTTPS2UQQS
- VCVTTSD2SIS
- VCVTTSD2USIS
- VCVTTSS2SIS
- VCVTTSS2USIS
- VDIVBF16
- VDPPHPS
- VFMADD132BF16
- VFMADD213BF16
- VFMADD231BF16
- VFMSUB132BF16
- VFMSUB213BF16
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETEXPBF16
- VGETMANTBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXPS
- VMINMAXSD
- VMINMAXSH
- VMINMAXSS
- VMOVD
- VMOVW
- VMPSADBW
- VMULBF16
- VPDPBSSD
- VPDPBSSDS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.