VFNMSUB132PH

VFNMSUB132PH computes -(op1 × op3) - op2 for each half-precision element and rounds once, writing over op1: both the product and the middle register are negated, and the destination and the operand that may come from memory, or be broadcast from one half, are the factors. VFNMSUB231PS shows for singles why this is not quite a negated VFMADD, with the signs of zero and the rounding direction; VFMADD132PH covers the FP16 family and what a merge mask keeps in each order, and VADDPH the format and the CPUID bits. The opcode is 9Eh with the 66 prefix in EVEX map 6. Rounding follows MXCSR.RC, or {er} on the 512-bit register form, and DAZ and FTZ are ignored (Intel’s optimization manual, Section 18.5.4).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles c[i] = -(a[i] * b[i]) - d[i] and c[i] = -(a[i] * b[i]) - c[i] over global _Float16 arrays to VFNMSUB132PH on zmm registers, reading a[i] from memory; Clang 23 uses VFNMSUB213PH on ymm registers with the subtracted array from memory. On three registers, _mm512_fnmsub_ph(a, b, c) and the zero-masking _mm512_maskz_fnmsub_ph split the same way, while _mm512_mask_fnmsub_ph(a, k, b, c), which must keep a where the mask is clear, is VFNMSUB132PH in both.

A loop that passes the running result back as the subtracted operand, acc = _mm512_fnmsub_ph(x, y, acc) with x and y loaded from arrays, takes VFNMSUB231PH in GCC. Clang unrolls it eight times and alternates: four VFNMSUB231PH into one register, then four VFNMSUB132PH that pass the value back and forth between two registers, each with y read from memory.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMSUB132PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fnmsub(a, c, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB132PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFMULCSH
• VFNMADD132PD
• VFNMADD132PH
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD

All 686 AVX10.1 instructions