VFNMSUB132SH instruction (AVX10.1)

VFNMSUB132SH computes -(op1 × op3) - op2 on the low halves and rounds once, writing over op1, a factor. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFNMSUB132PH; VFNMSUB213SH and VFNMSUB231SH are the other operand orders, VFMADD132SH explains what the scalar FMAs keep, and VFNMSUB132SS is the single-precision form. The encoding is 9Fh with the 66 prefix in EVEX map 6; it takes {er} between registers and reads two bytes from memory.

In our builds

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 compiles -(x * y) - z, __builtin_fmaf16(-x, y, -z) and _mm_fnmsub_sh(a, b, c) on _Float16 values to VFNMSUB132SH, Clang 23 to VFNMSUB213SH; with a factor from memory, -(x * a[5]) - z, both use VFNMSUB132SH.

GCC also compiles -(x * y + z) to VFNMSUB132SH, and the same expression on floats to VFNMSUB132SS, without -ffast-math. The two are not the same: when x × y + z is exactly zero, negating the sum gives -0, while the instruction computes -(x × y) - z, whose exact zero is +0 under round to nearest. For -(1 × 1) - (-1), rounding toward zero, Zen 5 returned +0 in VFNMSUB231PS, as that page shows. Clang 23 keeps VFMADD213SH and flips the sign with VXORPS, as both compilers do for -__builtin_fmaf16(x, y, z); with -ffast-math, which allows the sign of a zero to change, Clang folds the float version into VFNMSUB213SS but still not the half one.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMSUB132SH.

Forms

Every encoding of VFNMSUB132SH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFNMSUB132SH xmm {k}{z}, xmm, xmm, {er}` VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512	`EVEX.LIG.66.MAP6.W0 9F /r`	AVX10.1 or AVX512_FP16
`VFNMSUB132SH xmm {k}{z}, xmm, m16` VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512	`EVEX.LIG.66.MAP6.W0 9F /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm {k}{z}, xmm, xmm, {er}`no mask, with {er}	`xmm {k}{z}, xmm, xmm, {er}`with a mask, zeroing	`xmm {k}{z}, xmm, m16`
Sapphire Rapids	5 / 0.5p01	6 / 0.5p01	12 / 0.5p01

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low half is computed; the other halves come from xmm1.

The write mask k1 applies to the low half: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result half 0 is computed from half 0 of xmm1, xmm2 and xmm3; halves 7 to 1 are those of xmm1. Result halves 7 to 0: a7, a6, a5, a4, a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fnmsub(a, c, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Not run on a processor: none of these processors has AVX512-FP16. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFNMSUB132SH xmm {k}{z}, xmm, xmm/m16, {er}`
`xmm`	explicit	read, write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB132SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_fnmsub_sh` `__m128h _mm_fnmsub_sh(__m128h __W, __m128h __A, __m128h __B)`	`VFNMSUB132SH xmm, xmm, m16` EVEX.LIG -mavx512fp16when __A comes from memory
`_mm_mask_fnmsub_sh` `__m128h _mm_mask_fnmsub_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B)`	`VFNMSUB132SH xmm {k}, xmm, m16` EVEX.LIG -mavx512fp16when __A comes from memory
`_mm_maskz_fnmsub_sh` `__m128h _mm_maskz_fnmsub_sh(__mmask8 __U, __m128h __A, __m128h __B, __m128h __C)`	`VFNMSUB132SH xmm {k}{z}, xmm, m16` EVEX.LIG -mavx512fp16when __B comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

In our builds#