VFNMSUB213PD

VFNMSUB213PD computes -(op2 × op1) - op3 for each double, rounded once: the destination is a factor and the operand that may come from memory is subtracted. It is the double form of VFNMSUB213PS, and VFNMSUB231PS covers the doubly negated family. The VEX forms need the FMA extension; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask, a subtrahend of one double broadcast from memory and, in the 512-bit register form, a rounding mode given in the instruction.

In our builds#

At -O2 over double arrays, Clang 23 uses VFNMSUB213PD on ymm registers, with -march=x86-64-v3 and -v4, for w[i] = -(x[i] * y[i]) - z[i] and w[i] = -(x[i] * y[i]) - w[i], where GCC 14 takes VFNMSUB132PD; for w[i] = -(x[i] * k) - z[i] both use VFNMSUB213PD with z[i] from memory. With -ffast-math Clang moves the negations: that last loop becomes VFMSUB213PD with -k, and the polynomial 2 - (1 - (0.5 - 0.25 * t) * t) * t starts with VFMSUB213PD for 0.25t - 0.5 and continues with VFNMSUB213PD.

Signs of zero on Zen 5#

vfnmsub213pd zmm5{k2}, zmm5, zmm5, {rn-sae} computes -(x × x) - x, rounding to nearest. x = +0 gave -0, two negative zeros added, and x = -0 gave +0: -(+0) - (-0) is a zero sum of opposite signs, positive when rounding to nearest. x = 1 gave -2.

Under MXCSR 3FC0H (round down, DAZ), vfnmsub213pd xmm7, xmm11, xmm7 computed -(10^300 × -10^300) + 10^300 as the largest finite double, setting OE and PE, as rounding down stops a positive overflow.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        c = src3.f64[i]
        zmm1.f64[i] = fnmsub(b, a, c)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB213PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SS

All 60 FMA instructions

More AVX10.1 instructions

• VFNMADD132SH
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD

All 686 AVX10.1 instructions