VFNMSUB213PH

VFNMSUB213PH computes -(op2 × op1) - op3 for each half-precision element and rounds once, writing over op1: the destination is a factor, and the operand that may come from memory, or be broadcast from one half, is subtracted from the negated product. VFNMSUB132PH covers the negated subtracting FP16 forms, VFNMSUB231PS how they differ from a negated VFMADD, and VFNMSUB213PS is the single-precision form. The opcode is AEh with the 66 prefix in EVEX map 6; rounding follows MXCSR.RC, or {er} on the 512-bit register form, and denormals are kept whatever DAZ and FTZ say, as VADDPH explains.

Clang’s order#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 compiles c[i] = -(a[i] * b[i]) - d[i] over _Float16 arrays to VFNMSUB213PH on ymm registers, both factors loaded and d[i] read from memory, and _mm512_fnmsub_ph(a, b, c) on three registers too; GCC 14 uses VFNMSUB132PH for both, with a factor from memory in the loop.

A constant shows the compilers apart again. _mm512_fnmsub_ph(x, y, _mm512_set1_ph(1.0f16)) stays VFNMSUB213PH in GCC, with the half 1.0 broadcast from memory by {1to32}; Clang negates the constant and emits VFNMADD213PH with -1 broadcast instead, the same value -(x × y) - 1 rounded once.

Not a VFMADD with a sign flip#

-(x × y) - z and -(x × y + z) differ when x × y + z is exactly zero: the first gives +0 under round to nearest, the second -0, and under rounding up or down the two round in opposite directions. Neither compiler turns -_mm512_fmadd_ph(a, b, c) into this instruction: both keep VFMADD and flip the sign bits with an XOR.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMSUB213PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fnmsub(b, a, c)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB213PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PH
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS

All 686 AVX10.1 instructions